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    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE
    1.
    发明公开
    THREE-DIMENSIONAL SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240071910A1

    公开(公告)日：2024-02-29

    申请号：US18505998

    申请日：2023-11-09

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Sang Woo PARK ,  Dong Hyuk CHAE

    IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/528

    CPC分类号： H01L23/5226 ,  H01L21/76816 ,  H01L23/5283 ,  H10B69/00

    摘要： A three-dimensional semiconductor device may comprise a first cell region, a second cell region, and a via plug region disposed between the first cell region and the second cell region; a word line stack disposed in the first cell region, the via plug region, and the second cell region, the word line stack including a plurality of word lines and a plurality of interlayer insulating layers which are alternately stacked; and a plurality of via plugs exclusively connected to the plurality of the word lines, respectively, by vertically penetrating through the word line stack in the via plug region. The via plugs may have an arrangement of a zigzag pattern in a row direction from a top view. The diameters of the via plugs may increase in the row direction.

    MEMORY DEVICE HAVING VERTICAL STRUCTURE
    2.
    发明申请
    MEMORY DEVICE HAVING VERTICAL STRUCTURE 有权

    公开(公告)号：US20220122932A1

    公开(公告)日：2022-04-21

    申请号：US17210698

    申请日：2021-03-24

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Sang Woo PARK ,  Dong Hyuk CHAE ,  Ki Soo KIM

    IPC分类号： H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  G11C16/08

    摘要： A memory device having a vertical structure includes a memory cell array defined in a cell wafer, and having a plurality of word lines extending in a first direction and arranged in a second direction, and having a plurality of bit lines extending in the second direction and arranged in the first direction; and a logic circuit configured to control the memory cell array, and including a page buffer low-voltage circuit, a page buffer high-voltage circuit, a row decoder circuit and a peripheral circuit, wherein the page buffer low-voltage circuit is disposed in a first peripheral wafer and the page buffer high-voltage circuit, the row decoder circuit and the peripheral circuit are disposed in a second peripheral wafer, and wherein the cell wafer overlaps with the first peripheral wafer and the second peripheral wafer in a vertical direction that is perpendicular to a plane formed by the first direction and the second direction.

    MEMORY DEVICE
    6.
    发明申请
    MEMORY DEVICE 有权

    公开(公告)号：US20210366547A1

    公开(公告)日：2021-11-25

    申请号：US17015375

    申请日：2020-09-09

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Won Seok KIM ,  Sang Woo PARK

    IPC分类号： G11C16/08 ,  H01L25/18 ,  H01L23/00 ,  G11C16/14 ,  G11C16/24

    摘要： A memory device includes a first plane defined in a second wafer stacked on a first wafer; a second plane defined in a third wafer stacked on the second wafer, and overlapping with the first plane in a vertical direction; a first page buffer circuit including a first column driver coupled to bit lines of the first plane and a first column operator; and a second page buffer circuit including a second column driver coupled to bit lines of the second plane and a second column operator. The first column driver is disposed in the second wafer, the second column driver is disposed in the third wafer and overlaps with the first column driver in the vertical direction, and the first and second column operators are disposed in a cell region of the first wafer and overlap with the first and second planes in the vertical direction.

    SEMICONDUCTOR MEMORY DEVICE
    8.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20200373321A1

    公开(公告)日：2020-11-26

    申请号：US16708849

    申请日：2019-12-10

    申请人： SK hynix Inc.

    发明人： Sung Kwang KWAK ,  Sang Woo PARK ,  Chang Woon CHOI

    IPC分类号： H01L27/11575 ,  H01L27/11582 ,  H01L29/417 ,  H01L23/528

    摘要： A semiconductor memory device includes a memory cell array disposed on a source plate; a discharge plate disposed on a bottom surface of the source plate; a source line discharge circuit disposed on a substrate below the discharge plate, and electrically coupling the discharge plate to a ground node in response to a source line discharge control signal; and a discharge path provided between the discharge plate and the source line discharge circuit.

    MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND WRITE METHOD THEREOF
    9.
    发明申请
    MEMORY DEVICE, MEMORY SYSTEM HAVING THE SAME, AND WRITE METHOD THEREOF 有权

    公开(公告)号：US20220115357A1

    公开(公告)日：2022-04-14

    申请号：US17555383

    申请日：2021-12-18

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Ki Soo KIM ,  Sang Woo PARK ,  Dong Hyuk CHAE

    IPC分类号： H01L25/065 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/00 ,  G11C16/10 ,  G11C16/16 ,  G11C16/04

    摘要： A memory device includes: a first wafer including a first substrate, a plurality of first electrode layers and a plurality of first interlayer dielectric layers alternately stacked along first vertical channels projecting in a vertical direction on a top surface of the first substrate, and a dielectric stack comprising a plurality of dielectric layers and the plurality of first interlayer dielectric layers alternately stacked on the top surface of the first substrate; and a second wafer disposed on the first wafer, and including a second substrate, and a plurality of second electrode layers that are alternately stacked with a plurality of second interlayer dielectric layers along second vertical channels projecting in the vertical direction on a bottom surface of the second substrate and have pad parts overlapping with the dielectric stack in the vertical direction.

    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    THREE-DIMENSIONAL MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权

    公开(公告)号：US20220020764A1

    公开(公告)日：2022-01-20

    申请号：US17145229

    申请日：2021-01-08

    申请人： SK hynix Inc.

    发明人： Sung Lae OH ,  Jin Ho KIM ,  Sang Woo PARK ,  Sang Hyun SUNG

    IPC分类号： H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/768

    摘要： A three-dimensional memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate; a first stairway structure and a second stairway structure defined in the electrode structure, and positioned at different heights from each other; a sidewall of the electrode structure formed due to a difference in height between the first stairway structure and the second stairway structure; and a dielectric support passing through the electrode structure, and isolating a corner portion of the sidewall from the plurality of electrode layers.