公开(公告)号：US20140177358A1

公开(公告)日：2014-06-26

申请号：US13845293

申请日：2013-03-18

Applicant: SK hynix Inc.

Inventor： Young Suk MOON ,  Hyung Dong LEE ,  Yong Kee KWON ,  Hyung Gyun YANG

IPC: G11C8/04 ,  G11C7/10

CPC classification number: G11C8/04 ,  G11C7/1006 ,  G11C7/109

Abstract: A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die.

Abstract translation: 一种半导体装置，包括：第一存储管芯; 第二个记忆模具; 以及处理器，被配置为向第一存储管芯提供与读操作相关联的外部命令，外部起始地址和外部结束地址，并提供外部命令，外部起始地址和外部结束地址，其中 在存储在第一存储器管芯中的数据要被传送到第二存储器管芯并存储在第二存储器管芯中的情况下与第二存储器管芯相关联。

公开(公告)号：US20140143508A1

公开(公告)日：2014-05-22

申请号：US13844920

申请日：2013-03-16

Applicant: SK HYNIX INC.

Inventor： Yong Kee KWON ,  Hyung Dong LEE ,  Young Suk MOON ,  Hyung Gyun YANG

IPC: G06F12/00

CPC classification number: G06F12/00 ,  G06F3/0613 ,  G06F3/0635 ,  G06F3/0683 ,  G06F13/1626

Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory dies having different page sizes. The memory controller generates a plurality of chip selection signals for activating the plurality of memory dies based on the reordering number of requests received from a processor.

Abstract translation: 存储器系统包括存储器件和存储器控制器。 存储器件包括具有不同页面尺寸的多个存储器管芯。 存储器控制器基于从处理器接收的请求的重新排序数量来产生用于激活多个存储器管芯的多个芯片选择信号。

公开(公告)号：US20240403600A1

公开(公告)日：2024-12-05

申请号：US18507591

申请日：2023-11-13

Applicant: SK hynix Inc.

Inventor： Yong Kee KWON ,  Gu Hyun KIM ,  Nah Sung KIM ,  Chang Hyun KIM ,  Gyeong Cheol SHIN ,  Byeong Ju AN ,  Hae Rang CHOI

IPC: G06N3/042

Abstract: A processing-in-memory (PIM)-based accelerating device includes a plurality of PIM devices, a PIM network system configured to control traffic of signals and data for the plurality of PIM devices, and a first interface configured to perform interfacing with a host device. The PIM network system controls the traffic so that the plurality of PIM devices perform different operations, the plurality of PIM devices perform different operations in groups, or the plurality of PIM devices perform the same operation in parallel.

公开(公告)号：US20140181449A1

公开(公告)日：2014-06-26

申请号：US13943912

申请日：2013-07-17

Applicant: SK hynix Inc.

Inventor： Yong Kee KWON ,  Hyung Dong LEE ,  Young Suk MOON ,  Hyung Gyun YANG

IPC: G06F12/14

CPC classification number: G06F13/1631 ,  G06F12/0207 ,  G06F12/06 ,  G06F12/0623

Abstract: A memory system includes a memory unit and a memory controller. The memory unit includes a plurality of memory banks, wherein an information stored in a memory bank is accessed via a word line and a bit line. The memory controller is configured to limit repetitive accessing of a same word line or a same bit line so that the number of consecutive access is less than a predetermined critical value.

Abstract translation: 存储器系统包括存储器单元和存储器控制器。 存储单元包括多个存储体，其中通过字线和位线访问存储在存储体中的信息。 存储器控制器被配置为限制相同字线或相同位线的重复访问，使得连续访问的数量小于预定临界值。

公开(公告)号：US20140006863A1

公开(公告)日：2014-01-02

申请号：US13709644

申请日：2012-12-10

Applicant: SK HYNIX INC.

Inventor： Hyung Gyun YANG ,  Hyung Dong LEE ,  Yong Kee KWON ,  Young Suk MOON

IPC: G11C29/10

CPC classification number: G11C29/10 ,  G11C29/14 ,  G11C29/36

Abstract: A semiconductor memory apparatus includes a test circuit configured to receive a plurality of sequentially-changing test input patterns, compress the received test input patterns at each clock signal, and output the compressed patterns as variable test data.

Abstract translation: 一种半导体存储装置，包括被配置为接收多个顺序变化的测试输入模式的测试电路，在每个时钟信号处压缩所接收的测试输入模式，并输出压缩模式作为可变测试数据。

公开(公告)号：US20140006902A1

公开(公告)日：2014-01-02

申请号：US13711024

申请日：2012-12-11

Applicant: SK HYNIX INC.

Inventor： Hyung Gyun YANG ,  Hyung Dong LEE ,  Yong Kee KWON ,  Young Suk MOON

IPC: G11C29/42

CPC classification number: G11C29/42 ,  G11C29/4401 ,  G11C29/787 ,  G11C2029/0409 ,  G11C2029/0411

Abstract: Disclosed is a semiconductor device including an ECC circuit for improving error correction capability. A semiconductor device in accordance with an embodiment of the present invention includes a memory region configured to include a plurality of banks and a redundancy region within each of the banks and an error check and correction (ECC) region configured to detect an address of the memory region at which an error has occurred and correct a defect of the memory region by replacing the address at which the error has occurred with a redundancy line of the redundancy region based on address information.

Abstract translation: 公开了一种包括用于改善纠错能力的ECC电路的半导体器件。 根据本发明的实施例的半导体器件包括被配置为包括多个存储体的存储区域和每个存储体内的冗余区域以及被配置为检测存储器的地址的错误校验和校正（ECC）区域 基于地址信息，通过用冗余区域的冗余线代替发生错误的地址来校正存储区域的缺陷。

公开(公告)号：US20140006901A1

公开(公告)日：2014-01-02

申请号：US13720530

申请日：2012-12-19

Applicant: SK HYNIX INC.

Inventor： Young Suk MOON ,  Hyung Dong LEE ,  Yong Kee KWON ,  Hyung Gyun YANG

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048

Abstract: A memory system includes a processor and a plurality of memories. The processor includes a plurality of ECCs having different error restoration rates with each other, and a plurality of memories is coupled to the plurality of ECCs, respectively, according to distances from the processor.

Abstract translation: 存储器系统包括处理器和多个存储器。 处理器包括具有彼此具有不同错误恢复速率的多个ECC，并且多个存储器分别根据距处理器的距离耦合到多个ECC。