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公开(公告)号：US20220367567A1
公开(公告)日：2022-11-17
申请号：US17878678
申请日：2022-08-01
Applicant: SK hynix Inc.
Inventor： Si Jung YOO , Tae Hoon KIM , Hyung Dong LEE
Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
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公开(公告)号：US20210074767A1
公开(公告)日：2021-03-11
申请号：US16853386
申请日：2020-04-20
Applicant: SK hynix Inc.
Inventor： Hyung Dong LEE
IPC: H01L27/24 , H01L23/528 , H01L23/522
Abstract: A memory device includes first to nth decks respectively coupled to first to nth row lines which are stacked over a substrate in a vertical direction perpendicular to a surface of the substrate, n being a positive integer, a first connection structure extending from the substrate in the vertical direction to be coupled to the first row line, even-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of even-numbered row lines among the second to nth row lines, and odd-numbered connection structures extending from the substrate in the vertical direction and respectively coupled to ends of odd-numbered row lines among the second to nth row lines. The even-numbered connection structures are spaced apart from the odd-numbered connection structures with the first row line and the first connection structure that are interposed between the even-numbered connection structures and the odd-numbered connection structures.
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3.发明申请公开(公告)号：US20200027505A1
公开(公告)日：2020-01-23
申请号：US16296796
申请日：2019-03-08
Applicant: SK hynix Inc.
Inventor： Ki Won LEE , Seok Man HONG , Tae Hoon KIM , Hyung Dong LEE
IPC: G11C13/00
Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.
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公开(公告)号：US20250048651A1
公开(公告)日：2025-02-06
申请号：US18428376
申请日：2024-01-31
Applicant: SK hynix Inc.
Inventor： Yoon Mo KOO , Hyung Dong LEE
Abstract: A manufacturing method may include: forming first memory stack lines extending in a first direction; forming first access lines on the first memory stack lines to extend in a second direction intersecting the first direction, each first access line being electrically conductive to provide an electrical connection; forming a second memory stack on the first access lines; and forming first trenches extending between the first access lines to separate the second memory stack into second memory stack lines extending in the second direction, and to separate the first memory stack lines into first memory cells.
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公开(公告)号：US20170200888A1
公开(公告)日：2017-07-13
申请号：US15156966
申请日：2016-05-17
Applicant: SK hynix Inc.
Inventor： Hyung Dong LEE
IPC: H01L45/00
CPC classification number: H01L45/1233 , H01L27/2409 , H01L45/085 , H01L45/1266 , H01L45/145
Abstract: A switching device includes a first electrode and a second electrode, and an electrolyte layer disposed between the first electrode and the second electrode. The electrolyte layer includes a first layer charged with negative charges and a second layer charged with positive charges.
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Patent Agency Ranking
公开(公告)号：US20140177358A1
公开(公告)日：2014-06-26
申请号：US13845293
申请日：2013-03-18
Applicant: SK hynix Inc.
Inventor： Young Suk MOON , Hyung Dong LEE , Yong Kee KWON , Hyung Gyun YANG
CPC classification number: G11C8/04 , G11C7/1006 , G11C7/109
Abstract: A semiconductor apparatus includes a first memory die; a second memory die; and a processor configured to provide an external command, an external start address and an external end address which are associated with a read operation, to the first memory die, and provide an external command, an external start address and an external end address, which are associated with a write operation, to the second memory die, in the case where data stored in the first memory die is to be transferred to and stored in the second memory die.
Abstract translation: 一种半导体装置，包括：第一存储管芯; 第二个记忆模具; 以及处理器，被配置为向第一存储管芯提供与读操作相关联的外部命令，外部起始地址和外部结束地址，并提供外部命令，外部起始地址和外部结束地址，其中 在存储在第一存储器管芯中的数据要被传送到第二存储器管芯并存储在第二存储器管芯中的情况下与第二存储器管芯相关联。
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公开(公告)号：US20140143508A1
公开(公告)日：2014-05-22
申请号：US13844920
申请日：2013-03-16
Applicant: SK HYNIX INC.
Inventor： Yong Kee KWON , Hyung Dong LEE , Young Suk MOON , Hyung Gyun YANG
IPC: G06F12/00
CPC classification number: G06F12/00 , G06F3/0613 , G06F3/0635 , G06F3/0683 , G06F13/1626
Abstract: A memory system includes a memory device and a memory controller. The memory device includes a plurality of memory dies having different page sizes. The memory controller generates a plurality of chip selection signals for activating the plurality of memory dies based on the reordering number of requests received from a processor.
Abstract translation: 存储器系统包括存储器件和存储器控制器。 存储器件包括具有不同页面尺寸的多个存储器管芯。 存储器控制器基于从处理器接收的请求的重新排序数量来产生用于激活多个存储器管芯的多个芯片选择信号。
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公开(公告)号：US20210066393A1
公开(公告)日：2021-03-04
申请号：US16860686
申请日：2020-04-28
Applicant: SK hynix Inc.
Inventor： Si Jung YOO , Tae Hoon KIM , Hyung Dong LEE
Abstract: An electronic device includes a semiconductor memory including material layers each including one or more low-resistance areas and one or more high-resistance areas, insulating layers stacked alternately with the material layers and including protrusions extending more than the material layers, conductive pillars passing through the insulating layers and the low-resistance areas, conductive layers located between the protrusions, and variable resistance layers interposed between the low-resistance areas and the conductive layers.
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公开(公告)号：US20140006902A1
公开(公告)日：2014-01-02
申请号：US13711024
申请日：2012-12-11
Applicant: SK HYNIX INC.
Inventor： Hyung Gyun YANG , Hyung Dong LEE , Yong Kee KWON , Young Suk MOON
IPC: G11C29/42
CPC classification number: G11C29/42 , G11C29/4401 , G11C29/787 , G11C2029/0409 , G11C2029/0411
Abstract: Disclosed is a semiconductor device including an ECC circuit for improving error correction capability. A semiconductor device in accordance with an embodiment of the present invention includes a memory region configured to include a plurality of banks and a redundancy region within each of the banks and an error check and correction (ECC) region configured to detect an address of the memory region at which an error has occurred and correct a defect of the memory region by replacing the address at which the error has occurred with a redundancy line of the redundancy region based on address information.
Abstract translation: 公开了一种包括用于改善纠错能力的ECC电路的半导体器件。 根据本发明的实施例的半导体器件包括被配置为包括多个存储体的存储区域和每个存储体内的冗余区域以及被配置为检测存储器的地址的错误校验和校正（ECC）区域 基于地址信息，通过用冗余区域的冗余线代替发生错误的地址来校正存储区域的缺陷。
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公开(公告)号：US20140006901A1
公开(公告)日：2014-01-02
申请号：US13720530
申请日：2012-12-19
Applicant: SK HYNIX INC.
Inventor： Young Suk MOON , Hyung Dong LEE , Yong Kee KWON , Hyung Gyun YANG
IPC: G06F11/10
CPC classification number: G06F11/10 , G06F11/1048
Abstract: A memory system includes a processor and a plurality of memories. The processor includes a plurality of ECCs having different error restoration rates with each other, and a plurality of memories is coupled to the plurality of ECCs, respectively, according to distances from the processor.
Abstract translation: 存储器系统包括处理器和多个存储器。 处理器包括具有彼此具有不同错误恢复速率的多个ECC，并且多个存储器分别根据距处理器的距离耦合到多个ECC。
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