公开(公告)号：US20220101941A1

公开(公告)日：2022-03-31

申请号：US17203605

申请日：2021-03-16

Applicant: SK hynix Inc.

Inventor： Bo Ra KIM ,  Su Hae WOO ,  Jae Il LIM

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/36 ,  G11C29/14

Abstract: A memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to repair commands that control a self-repair operation of a memory device. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

公开(公告)号：US20220351801A1

公开(公告)日：2022-11-03

申请号：US17863773

申请日：2022-07-13

Applicant: SK hynix Inc.

Inventor： Bo Ra KIM ,  Su Hae WOO ,  Jae Il LIM

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/14 ,  G11C29/36

Abstract: A memory system includes a memory device and a memory controller. The memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to a plurality of repair commands. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

公开(公告)号：US20210375379A1

公开(公告)日：2021-12-02

申请号：US17039207

申请日：2020-09-30

Applicant: SK hynix Inc.

Inventor： Jae Il LIM ,  Du Hyun KIM ,  Bo Ra KIM ,  Sung Eun LEE

IPC: G11C29/38 ,  G11C29/44 ,  H01L25/065 ,  H01L25/18

Abstract: A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.