公开(公告)号：US20210119647A1

公开(公告)日：2021-04-22

申请号：US16910865

申请日：2020-06-24

Applicant: SK hynix Inc.

Inventor： Sung Eun LEE ,  Young Ook SONG

IPC: H03M13/29 ,  G06F11/10 ,  H03M13/00

Abstract: A parity generation logic circuit includes a first parity generation part and a second parity generation part. The first parity generation part is configured to generate a first parity in a first error correction mode having a first error correction capability for original data. The second parity generation part is configured to generate a second parity using the first parity in a second error correction mode having a second error correction capability.

公开(公告)号：US20210375379A1

公开(公告)日：2021-12-02

申请号：US17039207

申请日：2020-09-30

Applicant: SK hynix Inc.

Inventor： Jae Il LIM ,  Du Hyun KIM ,  Bo Ra KIM ,  Sung Eun LEE

IPC: G11C29/38 ,  G11C29/44 ,  H01L25/065 ,  H01L25/18

Abstract: A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.

公开(公告)号：US20180019007A1

公开(公告)日：2018-01-18

申请号：US15492182

申请日：2017-04-20

Applicant: SK hynix Inc.

Inventor： Sung Eun LEE ,  Jung Hyun KWON ,  Jae Sun LEE ,  JINGZHE XU

IPC: G11C7/10 ,  G06F13/16 ,  G11C11/406

CPC classification number: G11C7/1072 ,  G06F13/1663 ,  G06F13/1673 ,  G06F13/1684 ,  G11C7/10 ,  G11C7/1075 ,  G11C11/40607

Abstract: A data processing system may include a memory/storage circuit and a host. The memory/storage circuit may include a first memory module and a second memory module. Each of the first and second memory modules may include a controller and a memory device. The host may have access to the memory device of the first memory module and the memory device of the second memory module. Each of the controllers included in the first and second memory modules may be configured to selectively perform any one of a memory operation and a storage operation according to a request of the host.

公开(公告)号：US20180011754A1

公开(公告)日：2018-01-11

申请号：US15434314

申请日：2017-02-16

Applicant: SK hynix Inc.

Inventor： Jung Hyun KWON ,  Sung Eun LEE ,  Jae Sun LEE ,  Jingzhe XU

IPC: G06F11/07 ,  G06F3/06

CPC classification number: G06F11/0727 ,  G06F11/0793 ,  G06F11/1048

Abstract: A memory system may be provided. The memory system may include a memory apparatus including a plurality of memory cells. The memory system may include and a controller configured to control a write operation and a read operation with respect to the memory apparatus, detect an error occurrence position by performing the write operation and the read operation on a corresponding region of the memory apparatus in which an error occurs based on error occurrence address information generated in the read operation while changing a level of data to be written, and determine a type of error based on the detected error occurrence position.

公开(公告)号：US20170237442A1

公开(公告)日：2017-08-17

申请号：US15190495

申请日：2016-06-23

Applicant: SK hynix Inc.

Inventor： Kyung Hoon KIM ,  Myeong Jae PARK ,  Woo Yeol SHIN ,  Sung Eun LEE ,  Han Kyu CHI ,  Jae Won HAN

IPC: H03L7/07 ,  H03L7/091 ,  H03M9/00 ,  H03L7/081

CPC classification number: H03L7/07 ,  G11C7/1093 ,  G11C7/222 ,  H03L7/0805 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/091 ,  H03M9/00

Abstract: A clock generation circuit may be provided. The clock generation circuit may include a master DLL (Delay Locked Loop) circuit, a code divider and a slave DLL circuit. The master DLL may generate a phase pulse signal having a pulse width corresponding to one cycle of a clock signal, and may generate a delay control code corresponding to the phase pulse signal. The code divider may generate a divided delay control code corresponding to a predetermined time by dividing the delay control code. The slave DLL circuit may generate a delayed strobe signal by delaying a strobe signal according to the divided delay control code.