公开(公告)号：US09941253B1

公开(公告)日：2018-04-10

申请号：US15597484

申请日：2017-05-17

Applicant: Sk hynix Inc.

Inventor： Yeon Seung Jung ,  Jin Woo Park ,  Joo Wan Hong

IPC: H01L25/065 ,  H01L23/538 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/538 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06544 ,  H01L2225/06568 ,  H01L2225/06582 ,  H01L2924/15311

Abstract: A semiconductor package and or method of fabricating a semiconductor package may be provided. The semiconductor package may include a package substrate. The semiconductor package may include a first semiconductor die coupled to the package substrate by first interconnectors. The semiconductor package may include a second semiconductor die coupled to the first semiconductor die by second interconnectors. The second semiconductor die may be coupled to the substrate.

公开(公告)号：US11342315B2

公开(公告)日：2022-05-24

申请号：US16184741

申请日：2018-11-08

Applicant: SK hynix Inc.

Inventor： Juil Eom ,  Bok Kyu Choi ,  Jae Hoon Lee ,  Jin Woo Park

IPC: H01L25/10 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L23/498

Abstract: A stack package includes a first sub-package and a second sub-package stacked on the first sub-package. The first sub-package includes a first through mold via (TMV) for connection spaced apart from a first semiconductor chip in an X-axis direction, a first TMV for bypass spaced apart from the first semiconductor chip in a Y-axis direction, and a first redistribution line (RDL) pattern connecting the first semiconductor chip to the first TMV for connection. The second sub-package includes a second TMV for connection spaced apart from a second semiconductor chip in the Y-axis direction and another RDL pattern connecting the second semiconductor chip to the second TMV for connection. the second sub-package is stacked on the first sub-package such that the second TMV for connection is connected to the first TMV for bypass.

公开(公告)号：US09117938B2

公开(公告)日：2015-08-25

申请号：US14180327

申请日：2014-02-13

Applicant: SK HYNIX INC.

Inventor： Jin Woo Park ,  Sang Gyu Lee

IPC: H01L23/52 ,  H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L25/065 ,  H01L21/784 ,  H01L23/31 ,  H01L25/18

CPC classification number: H01L24/97 ,  H01L21/7684 ,  H01L21/76897 ,  H01L21/76898 ,  H01L21/784 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/481 ,  H01L24/05 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L24/81 ,  H01L24/92 ,  H01L24/94 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/05009 ,  H01L2224/05605 ,  H01L2224/05609 ,  H01L2224/05611 ,  H01L2224/05613 ,  H01L2224/05616 ,  H01L2224/05618 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13025 ,  H01L2224/13082 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2224/16146 ,  H01L2224/16148 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/92225 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06544 ,  H01L2225/06548 ,  H01L2225/06565 ,  H01L2225/06568 ,  H01L2924/1431 ,  H01L2924/1436 ,  H01L2924/1437 ,  H01L2924/1438 ,  H01L2924/1441 ,  H01L2924/15311 ,  H01L2924/157 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2924/00

Abstract: A semiconductor device includes a via electrode penetrating a substrate and a back-side molding layer covering a back-side surface of the substrate. The back-side molding layer contacts a sidewall of a back-side end portion of the via electrode, which is a portion of the via electrode that protrudes from the back-side surface of the substrate.

Abstract translation: 半导体器件包括穿透基板的通路电极和覆盖基板的背面的背面成型层。 背面成型层与作为从基板的背面突出的通孔电极的一部分的通路电极的背面侧端部的侧壁接触。

公开(公告)号：US10361141B2

公开(公告)日：2019-07-23

申请号：US16017118

申请日：2018-06-25

Applicant: SK hynix Inc.

Inventor： Yeon Seung Jung ,  Jong Hoon Kim ,  Jin Woo Park

IPC: H01L23/367 ,  H01L23/00 ,  H01L21/768 ,  H05K1/02

Abstract: A semiconductor package and a method of manufacturing the semiconductor package may be provided. The semiconductor package may include a first semiconductor chip disposed on a first surface of an interconnection layer, a second and a third semiconductor chips disposed on a second surface of the interconnection layer. The semiconductor package may include a thermal transfer plate disposed between the second and third semiconductor chips, contacting the second surface of the interconnection layer, and overlapping with the first semiconductor chip. The thermal transfer plate may be configured to provide a heat radiation path.

公开(公告)号：US09536846B2

公开(公告)日：2017-01-03

申请号：US14526073

申请日：2014-10-28

Applicant: SK hynix Inc.

Inventor： Jin Woo Park ,  Sung Su Park ,  Bae Yong Kim

IPC: H01L23/00 ,  H01L23/48 ,  H01L21/768 ,  H01L21/683

CPC classification number: H01L24/05 ,  H01L21/6835 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/034 ,  H01L2224/0361 ,  H01L2224/03614 ,  H01L2224/03912 ,  H01L2224/0401 ,  H01L2224/05017 ,  H01L2224/051 ,  H01L2224/05138 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05647 ,  H01L2224/11002 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13022 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/14181 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01014 ,  H01L2924/012

Abstract: A semiconductor device includes a chip body having an uneven surface including at least two regions at different levels from one another, a through electrode penetrating the chip body and having an end which is exposed by the uneven surface of the chip body, a passivation layer disposed on the uneven surface of the chip body, and a bump disposed on the passivation layer and the exposed end of the through electrode and overlapping with the uneven surface of the chip body.

Abstract translation: 一种半导体器件包括：芯片本体，具有包括彼此不同的至少两个区域的不平坦表面;穿透芯片本体并具有由芯片体的不平坦表面露出的端部的贯通电极，设置有钝化层 并且设置在钝化层和通孔的露出端上并与芯片体的不平坦表面重叠的凸起。