公开(公告)号：US20220005820A1

公开(公告)日：2022-01-06

申请号：US17145209

申请日：2021-01-08

申请人： SK hynix Inc.

发明人： Jin Ho KIM ,  Kwang Hwi PARK ,  Sang Hyun SUNG ,  Sung Lae OH ,  Chang Woon CHOI

IPC分类号： H01L27/11556 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/11573

摘要： A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

公开(公告)号：US20210183770A1

公开(公告)日：2021-06-17

申请号：US16876008

申请日：2020-05-16

申请人： SK hynix Inc.

发明人： Jeong Hwan KIM ,  Jin Ho KIM ,  Byung Hyun JUN ,  Chang Woon CHOI

IPC分类号： H01L23/535 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11573 ,  H01L23/522 ,  H01L23/528

摘要： A semiconductor memory device includes a cell region defined with vertical channels which pass through electrode layers and interlayer dielectric layers alternately stacked; a step region disposed adjacent to the cell region in a first direction, and defined with contacts coupled to the electrode layers extending in different lengths; a first opening passing through the electrode layers and the interlayer dielectric layers in the step region; a second opening passing through the electrode layers and the interlayer dielectric layers in the cell region; under wiring lines coupled with a peripheral circuit defined on a substrate; top wiring lines disposed over the electrode layers and the interlayer dielectric layers, and coupled with the contacts; and vertical vias coupling the under and top wiring lines, wherein the vertical vias include first vertical vias which pass through the first opening and second vertical vias which pass through the second opening.

公开(公告)号：US20220293619A1

公开(公告)日：2022-09-15

申请号：US17828417

申请日：2022-05-31

申请人： SK hynix Inc.

发明人： Jin Ho KIM ,  Kwang Hwi PARK ,  Sang Hyun SUNG ,  Sung Lae OH ,  Chang Woon CHOI

IPC分类号： H01L27/11556 ,  H01L27/11573 ,  H01L27/11582 ,  H01L27/11526

摘要： A memory device includes a cell wafer including a memory cell array; and a peripheral wafer including a row control circuit, a column control circuit and a peripheral circuit which control the memory cell array, and stacked on and bonded to the cell wafer in a first direction. The peripheral wafer includes a first substrate having a first surface and a second surface which face away from each other in the first direction; a first logic structure disposed on the first surface of the first substrate, and including the row control circuit and the column control circuit; and a second logic structure disposed on the second surface of the first substrate, and including the peripheral circuit.

公开(公告)号：US20210036007A1

公开(公告)日：2021-02-04

申请号：US16779599

申请日：2020-02-01

申请人： SK hynix Inc.

发明人： Sung Lae OH ,  Jin Ho KIM ,  Sang Woo PARK ,  Sang Hyun SUNG ,  Soo Nam JUNG ,  Chang Woon CHOI

IPC分类号： H01L27/11582 ,  H01L21/768 ,  H01L23/00 ,  H01L27/11556 ,  H01L21/311 ,  H01L27/11573 ,  H01L21/033 ,  H01L29/66 ,  H01L23/528 ,  H01L21/02 ,  H01L27/11526 ,  H01L25/18

摘要： A semiconductor memory device includes an electrode structure including a plurality of electrode layers and a plurality of interlayer dielectric layers which are alternately stacked on a substrate defined with a plurality of cell areas and a plurality of coupling areas in a first direction; a hard mask pattern disposed on the electrode structure, and having a plurality of opening holes in the coupling areas; and a plurality of contact holes defined in the electrode structure under the plurality of opening holes, and exposing pad areas of the electrode layers, respectively. The plurality of opening holes are disposed by being distributed in a plurality of rows arranged in a second direction intersecting with the first direction.

公开(公告)号：US20200373321A1

公开(公告)日：2020-11-26

申请号：US16708849

申请日：2019-12-10

申请人： SK hynix Inc.

发明人： Sung Kwang KWAK ,  Sang Woo PARK ,  Chang Woon CHOI

IPC分类号： H01L27/11575 ,  H01L27/11582 ,  H01L29/417 ,  H01L23/528

摘要： A semiconductor memory device includes a memory cell array disposed on a source plate; a discharge plate disposed on a bottom surface of the source plate; a source line discharge circuit disposed on a substrate below the discharge plate, and electrically coupling the discharge plate to a ground node in response to a source line discharge control signal; and a discharge path provided between the discharge plate and the source line discharge circuit.