公开(公告)号：US20150071009A1

公开(公告)日：2015-03-12

申请号：US14106794

申请日：2013-12-15

Applicant: SK hynix Inc.

Inventor： Kie-Bong KU ,  Hye-Young LEE ,  Sung-Hwa OK ,  Se-Jin YOO

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1087 ,  G11C7/1006 ,  G11C7/227

Abstract: A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode.

Abstract translation: 半导体器件包括：数据总线反转（DBI）判定单元，用于根据读取的数据判定是否执行DBI操作模式，并且生成对应于判定结果的DBI判定信号; 输出控制单元，其适于产生在DBI操作模式中反映出所述判定的延迟时间量的布置控制信号; 数据同步单元，其适于使读取数据与布置控制信号同步，并以DBI运行模式输出同步读数据和同步读数据的反相信号; 以及数据输出单元，其适于在DBI操作模式中响应于DBI判定信号，布置控制信号和输出控制信号，选择性地将同步读取数据和同步读取数据的反相信号输出到外部。

公开(公告)号：US20130339641A1

公开(公告)日：2013-12-19

申请号：US13717552

申请日：2012-12-17

Applicant: SK HYNIX INC.

Inventor： Sung-Hwa OK ,  Kie-Bong KU ,  Hye-Young LEE ,  Sejin YOO

IPC: G06F12/06

CPC classification number: G06F12/0646 ,  G11C7/1009 ,  G11C7/1045

Abstract: A memory device includes a pad that provides an interface with an exterior, a first setting unit that generates a termination setting signal for setting the pad for a purpose of termination data strobe using a first specific code of a mode register set operation, a second setting unit that generates a mask setting signal for setting the pad for a purpose of data mask using a second specific code of the mode register set operation, and a third setting unit that generates a write inversion setting signal for setting the pad for a purpose of write data bus inversion using third specific code of the mode register set operation. When a setting signal with a higher priority is activated, a setting signal with a lower priority is deactivated regardless of a value of the corresponding code.

Abstract translation: 存储装置包括提供与外部的接口的焊盘，第一设置单元，其使用模式寄存器设置操作的第一特定代码生成终止数据选通目的的设置焊盘的终止设置信号，第二设置 单元，其使用模式寄存器设置操作的第二特定代码产生用于设置数据掩码的掩模的掩模设置信号;以及第三设置单元，其产生用于设置用于写入的目的的焊盘的写入反转设置信号 数据总线反转使用模式寄存器集合操作的第三个特定代码。 当激活具有较高优先级的设置信号时，不管相应代码的值如何，具有较低优先级的设置信号被去激活。

公开(公告)号：US20150016201A1

公开(公告)日：2015-01-15

申请号：US14090945

申请日：2013-11-26

Applicant: SK hynix Inc.

Inventor： Hye-Young LEE ,  Kie-Bong KU ,  Choung-Ki SONG ,  Sung-Hwa OK ,  Se-Jin YOO

IPC: G11C7/10

CPC classification number: G11C7/1006 ,  G11C7/1012 ,  G11C11/4093 ,  G11C11/4097 ,  G11C2207/005 ,  G11C2207/105

Abstract: A semiconductor device includes first and second bank groups coupled to first and second data lines which are electrically isolated from each other. The semiconductor device includes a register unit suitable for providing predetermined data to the second data line in a specific mode, a data transfer and output unit suitable for externally outputting the predetermined data loaded onto the second data line and simultaneously transferring the predetermined data to the first data line in the specific mode, and a data output unit suitable for externally outputting the predetermined data loaded onto the first data line in the specific mode.

Abstract translation: 半导体器件包括耦合到彼此电绝缘的第一和第二数据线的第一和第二组组。 该半导体器件包括适于在特定模式中向第二数据线提供预定数据的寄存器单元，适于外部输出加载到第二数据线上的预定数据的数据传输和输出单元，并同时将预定数据传送到第一数据线 数据线，以及适于在特定模式中外加输出加载到第一数据线上的预定数据的数据输出单元。