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公开(公告)号：US20150310935A1
公开(公告)日：2015-10-29
申请号：US14792167
申请日：2015-07-06
Applicant: SK hynix Inc.
Inventor： Kie-Bong KU
CPC classification number: G06F11/0727 , G06F11/0772 , G06F11/0784 , G11C29/38 , G11C29/42 , G11C29/44 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.
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公开(公告)号：US20140003173A1
公开(公告)日：2014-01-02
申请号：US13716362
申请日：2012-12-17
Applicant: SK HYNIX INC.
Inventor： Kie-Bong KU
IPC: G11C29/04
CPC classification number: G11C11/4097 , G11C5/025 , G11C7/18 , G11C8/14 , G11C29/025 , G11C29/04 , G11C29/808
Abstract: A memory cell array includes a plurality of normal word lines arranged at a first pitch, a plurality of repair word lines arranged at a second pitch, and a dummy boundary word line configured to be arranged between an outermost normal word line and an outermost repair word line.
Abstract translation: 存储单元阵列包括以第一间距布置的多个正常字线，以第二间距排列的多个修补字线，以及配置为布置在最外侧正常字线和最外侧修复字之间的虚拟边界字线 线。
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公开(公告)号：US20160155483A1
公开(公告)日：2016-06-02
申请号：US15018017
申请日：2016-02-08
Applicant: SK hynix Inc.
Inventor： Kie-Bong KU
IPC: G11C7/10
CPC classification number: G11C7/1039 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , H03K3/0375
Abstract: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal
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公开(公告)号：US20150084665A1
公开(公告)日：2015-03-26
申请号：US14556019
申请日：2014-11-28
Applicant: SK hynix Inc.
Inventor： Kie-Bong KU , Lee-Bum LEE
IPC: G01R31/26
CPC classification number: G01R31/26 , G01R31/2834 , G11C29/08 , G11C29/44 , G11C29/50
Abstract: A method for testing a semiconductor device includes testing the semiconductor device in a plurality of operation modes sequentially, and programming the semiconductor device to operate in at least one of the operation modes when the semiconductor device passes the testing.
Abstract translation: 一种用于测试半导体器件的方法包括：以半导体器件通过测试，依次以多种操作模式对半导体器件进行测试，以及对半导体器件进行编程以在至少一种操作模式下工作。
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公开(公告)号：US20130339641A1
公开(公告)日：2013-12-19
申请号：US13717552
申请日：2012-12-17
Applicant: SK HYNIX INC.
Inventor： Sung-Hwa OK , Kie-Bong KU , Hye-Young LEE , Sejin YOO
IPC: G06F12/06
CPC classification number: G06F12/0646 , G11C7/1009 , G11C7/1045
Abstract: A memory device includes a pad that provides an interface with an exterior, a first setting unit that generates a termination setting signal for setting the pad for a purpose of termination data strobe using a first specific code of a mode register set operation, a second setting unit that generates a mask setting signal for setting the pad for a purpose of data mask using a second specific code of the mode register set operation, and a third setting unit that generates a write inversion setting signal for setting the pad for a purpose of write data bus inversion using third specific code of the mode register set operation. When a setting signal with a higher priority is activated, a setting signal with a lower priority is deactivated regardless of a value of the corresponding code.
Abstract translation: 存储装置包括提供与外部的接口的焊盘，第一设置单元，其使用模式寄存器设置操作的第一特定代码生成终止数据选通目的的设置焊盘的终止设置信号，第二设置 单元，其使用模式寄存器设置操作的第二特定代码产生用于设置数据掩码的掩模的掩模设置信号;以及第三设置单元，其产生用于设置用于写入的目的的焊盘的写入反转设置信号 数据总线反转使用模式寄存器集合操作的第三个特定代码。 当激活具有较高优先级的设置信号时，不管相应代码的值如何，具有较低优先级的设置信号被去激活。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20150100837A1
公开(公告)日：2015-04-09
申请号：US14106798
申请日：2013-12-15
Applicant: SK hynix Inc.
Inventor： Kie-Bong KU
IPC: G06F11/20
CPC classification number: G06F11/2094 , G06F11/1048 , G11C29/42 , G11C29/4401 , G11C29/78 , G11C2029/0409 , G11C2029/4402
Abstract: A semiconductor memory device includes a memory cell array including a normal region for storing a plurality of data, an error information region for storing a plurality of error information data corresponding to the plurality of normal data, respectively, and a redundancy region for replacing the normal region, an error detection unit suitable for detecting an error on the plurality of data in response to the plurality of error information data, and storing an error location information, which indicates a storage region of a data having an error in the normal and redundancy regions, based on an error detection result, and a repair operation unit suitable for replacing the storage region, which is indicated by the error location information, by the redundancy region during a repair operation period.
Abstract translation: 一种半导体存储器件，包括存储单元阵列，该存储单元阵列包括用于存储多个数据的法线区域，分别存储与该多个正常数据对应的多个误差信息数据的误差信息区域，以及用于替换正常 区域，适合于响应于所述多个错误信息数据来检测所述多个数据上的错误的错误检测单元，以及存储指示在正常和冗余区域中具有错误的数据的存储区域的错误位置信息 以及修复操作单元，其适于在修复操作期间由冗余区域替换由错误位置信息指示的存储区域。
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公开(公告)号：US20150098283A1
公开(公告)日：2015-04-09
申请号：US14106821
申请日：2013-12-15
Applicant: SK hynix Inc.
Inventor： Kie-Bong KU
CPC classification number: G11C7/1039 , G11C7/1051 , G11C7/1057 , G11C7/106 , G11C7/1078 , G11C7/1087 , G11C7/1093 , G11C7/22 , H03K3/0375
Abstract: A semiconductor device includes a pipe latch suitable for sequentially latching data in response to a pipe input control signal and sequentially outputting data in response to a pipe output control signal, a pipe latch control unit suitable for generating the pipe input/output control signals in response to a command signal and latency information, and resetting the pipe input/output control signals in response to a pipe reset signal, and an error detection unit suitable for receiving the pipe input control signal and the pipe output control signal, detecting a latency error, and generating the pipe reset signal
Abstract translation: 一种半导体装置，包括适于响应于管道输入控制信号顺序地锁存数据并且响应于管道输出控制信号顺序地输出数据的管道锁存器，适于响应地产生管道输入/输出控制信号的管道锁存器控制单元 指令信号和延迟信息，以及响应于管道复位信号复位管道输入/输出控制信号;以及错误检测单元，适于接收管道输入控制信号和管道输出控制信号，检测延迟误差， 并产生管道复位信号
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公开(公告)号：US20150071009A1
公开(公告)日：2015-03-12
申请号：US14106794
申请日：2013-12-15
Applicant: SK hynix Inc.
Inventor： Kie-Bong KU , Hye-Young LEE , Sung-Hwa OK , Se-Jin YOO
CPC classification number: G11C7/1087 , G11C7/1006 , G11C7/227
Abstract: A semiconductor device includes a data bus inversion (DBI) decision unit suitable for deciding whether a DBI operation mode is performed, based on a read data, and generating a DBI decision signal corresponding to a result of the decision; an output control unit suitable for generating an arrangement control signal in which a delay amount of time for the decision is reflected, in a DBI operation mode; a data synchronization unit suitable for synchronizing the read data with the arrangement control signal and output the synchronized read data and inverted signals of the synchronized read data, in the DBI operation mode; and a data output unit suitable for selectively outputting the synchronized read data and the inverted signals of the synchronized read data, to an external in response to the DBI decision signal, the arrangement control signal and an output control signal, in the DBI operation mode.
Abstract translation: 半导体器件包括：数据总线反转（DBI）判定单元，用于根据读取的数据判定是否执行DBI操作模式，并且生成对应于判定结果的DBI判定信号; 输出控制单元，其适于产生在DBI操作模式中反映出所述判定的延迟时间量的布置控制信号; 数据同步单元，其适于使读取数据与布置控制信号同步，并以DBI运行模式输出同步读数据和同步读数据的反相信号; 以及数据输出单元，其适于在DBI操作模式中响应于DBI判定信号，布置控制信号和输出控制信号，选择性地将同步读取数据和同步读取数据的反相信号输出到外部。
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公开(公告)号：US20140003170A1
公开(公告)日：2014-01-02
申请号：US13716394
申请日：2012-12-17
Applicant: SK HYNIX INC.
Inventor： Kie-Bong KU
CPC classification number: G01R31/318555 , G01R31/041 , G01R31/046 , G01R31/2884 , G01R31/318572 , G11C5/14 , G11C29/00 , G11C29/022 , G11C29/46 , G11C29/48 , G11C29/54
Abstract: An integrated circuit chip includes a test enable pad configured to receive a test enable signal, a plurality of test input pads including a reset pad, a signal combination unit configured to combine signals input to the plurality of test input pads when the test enable signal is activated, and to generate a plurality of test output signals, a plurality of test output pads configured to output the plurality of test output signals, and a reset control unit configured to generate a system reset signal using a signal input to the reset pad when the test enable signal is deactivated, and to generate the system reset signal using the test enable signal when the test enable signal is activated.
Abstract translation: 集成电路芯片包括被配置为接收测试使能信号的测试使能焊盘，包括复位焊盘的多个测试输入焊盘，被配置为当测试使能信号为...时，组合输入到多个测试输入焊盘的信号的信号组合单元 激活并产生多个测试输出信号，多个测试输出焊盘，被配置为输出多个测试输出信号;以及复位控制单元，其被配置为使用输入到复位焊盘的信号来产生系统复位信号 测试使能信号被禁用，并且当测试使能信号被激活时，使用测试使能信号产生系统复位信号。
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公开(公告)号：US20150310936A1
公开(公告)日：2015-10-29
申请号：US14792203
申请日：2015-07-06
Applicant: SK hynix Inc.
Inventor： Kie-Bong KU
CPC classification number: G06F11/0727 , G06F11/0772 , G06F11/0784 , G11C29/38 , G11C29/42 , G11C29/44 , G11C29/52 , G11C2029/0409 , G11C2029/0411
Abstract: A semiconductor memory device includes a plurality of data input/output pads configured to transmit and receive data to and from memory cells, an alert pad configured to output data error information while the data is transmitted and received, and a monitoring device configured to output the data error information to the alert pad in a first mode and to output monitoring information to the alert pad in a second mode.
Abstract translation: 一种半导体存储器件，包括多个数据输入/输出焊盘，被配置为向存储器单元发送数据和从存储器单元接收数据;警报焊盘，被配置为在发送和接收数据的同时输出数据错误信息;以及监视装置， 数据错误信息以第一模式发送到警报器，并且在第二模式中将监视信息输出到警报器。
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