公开(公告)号：US11424003B2

公开(公告)日：2022-08-23

申请号：US17203605

申请日：2021-03-16

Applicant: SK hynix Inc.

Inventor： Bo Ra Kim ,  Su Hae Woo ,  Jae Il Lim

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/14 ,  G11C29/36

Abstract: A memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to repair commands that control a self-repair operation of a memory device. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

公开(公告)号：US12242736B1

公开(公告)日：2025-03-04

申请号：US18404891

申请日：2024-01-05

Applicant: SK hynix Inc.

Inventor： Jae Il Lim ,  Jae Won Chung

IPC: G06F3/06

Abstract: A memory controller includes a command/address generation module; and a row-hammer tracking module configured to track a row-hammer address based on an active command and an address for a target bank and a target row indicated by the active command, the active command and the address being received from the command/address generation module, wherein the row-hammer tracking module includes: a plurality of storage devices each including fields corresponding to banks, each of the fields storing candidate addresses and access counting values for the candidate addresses; and at least one search controller configured to sequentially search, according to a clock, fields of the plurality of storage devices corresponding to the target bank when the active command is input, and search, during one clock, fields of the plurality of storage devices corresponding to different banks based on active commands indicating the different banks.

公开(公告)号：US11651831B2

公开(公告)日：2023-05-16

申请号：US17039207

申请日：2020-09-30

Applicant: SK hynix Inc.

Inventor： Jae Il Lim ,  Du Hyun Kim ,  Bo Ra Kim ,  Sung Eun Lee

IPC: G11C29/38 ,  G11C29/44 ,  H01L25/18 ,  H01L25/065 ,  G11C29/54

CPC classification number: G11C29/38 ,  G11C29/4401 ,  H01L25/0652 ,  H01L25/18 ,  H01L2225/06513 ,  H01L2225/06541

Abstract: A memory system includes a memory device including a plurality of banks, each including row and column spares for replacing defective rows and columns; and a memory controller suitable for controlling an operation of the memory device, wherein the memory controller includes: a built-in self-test (BIST) circuit suitable for performing a test operation on the banks and generating fail addresses for each bank based on a result of the test operation; and a built-in redundancy analysis (BIRA) circuit suitable for determining first and second spare counts by respectively counting the number of repairable row spares and repairable column spares, and selecting a target repair address from the fail addresses for each bank, according to the first and second spare counts.

公开(公告)号：US11621050B2

公开(公告)日：2023-04-04

申请号：US17024396

申请日：2020-09-17

Applicant: SK hynix Inc.

Inventor： Jae Il Lim ,  Su Hae Woo

IPC: G11C29/44 ,  G11C29/38 ,  G06F11/20 ,  G11C29/16 ,  G11C29/00

Abstract: A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.

公开(公告)号：US11804278B2

公开(公告)日：2023-10-31

申请号：US17863773

申请日：2022-07-13

Applicant: SK hynix Inc.

Inventor： Bo Ra Kim ,  Su Hae Woo ,  Jae Il Lim

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/14 ,  G11C29/36

CPC classification number: G11C29/44 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C2029/4402

Abstract: A memory system includes a memory device and a memory controller. The memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to a plurality of repair commands. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.