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    Semiconductor memory devices and repair methods of the semiconductor memory devices
    1.
    发明授权
    Semiconductor memory devices and repair methods of the semiconductor memory devices 有权

    公开(公告)号：US11621050B2

    公开(公告)日：2023-04-04

    申请号：US17024396

    申请日：2020-09-17

    Applicant: SK hynix Inc.

    Inventor： Jae Il Lim ,  Su Hae Woo

    IPC: G11C29/44 ,  G11C29/38 ,  G06F11/20 ,  G11C29/16 ,  G11C29/00

    Abstract: A semiconductor memory device includes a memory and a memory controller configured to control the memory. The memory controller includes a normal operation control part and a repair part. The normal operation control part is configured to control a normal operation of the memory and includes a plurality of storage spaces used while the normal operation is controlled. The repair part is configured to control a repair operation of the memory and stores faulty addresses detected while the repair operation is controlled into the plurality of storage spaces included in the normal operation control part.

    Module controllers for memory devices and memory modules including the module controllers
    2.
    发明授权
    Module controllers for memory devices and memory modules including the module controllers 有权

    公开(公告)号：US10861577B2

    公开(公告)日：2020-12-08

    申请号：US16205747

    申请日：2018-11-30

    Applicant: SK hynix Inc.

    Inventor： Su Hae Woo

    IPC: G11C29/44 ,  G11C29/42 ,  G11C29/52 ,  G06F11/10

    Abstract: A test circuit includes a built-in self-test (BIST) circuit and a built-in repair analysis (BIRA) circuit. The built-in self-test (BIST) circuit performs a test operation for a plurality of memory packages to generate fail information. The built-in repair analysis (BIRA) circuit receives the fail information from the BIST circuit to select at least one of the plurality of memory packages as a repair target memory package. The repair target memory package is selected by considering an error correction capability of an error correction code (ECC) circuit and usability of redundancy regions included in each of the plurality of memory packages.

    Memory systems including simplified BISR logic circuit
    3.
    发明授权
    Memory systems including simplified BISR logic circuit 有权

    公开(公告)号：US11804278B2

    公开(公告)日：2023-10-31

    申请号：US17863773

    申请日：2022-07-13

    Applicant: SK hynix Inc.

    Inventor： Bo Ra Kim ,  Su Hae Woo ,  Jae Il Lim

    IPC: G11C29/44 ,  G11C29/42 ,  G11C29/14 ,  G11C29/36

    CPC classification number: G11C29/44 ,  G11C29/14 ,  G11C29/36 ,  G11C29/42 ,  G11C2029/4402

    Abstract: A memory system includes a memory device and a memory controller. The memory controller includes a core processor and a built-in self-repair (BISR) logic circuit. The core processor includes a register file with a plurality of register values corresponding to a plurality of repair commands. The BISR logic circuit receives at least one of the plurality of register values from the core processor and converts the at least one of the plurality of register values into at least one of the repair commands to output the least one of the repair commands to the memory device. The core processor transmits the at least one of the plurality of register values to the BISR logic circuit in response to a firmware instruction that is output from an external firmware coupled to the memory controller.

    Semiconductor system including a counting circuit block
    4.
    发明授权
    Semiconductor system including a counting circuit block 有权

    公开(公告)号：US10679691B2

    公开(公告)日：2020-06-09

    申请号：US16203350

    申请日：2018-11-28

    Applicant: SK hynix Inc.

    Inventor： Seung Gyu Jeong ,  Do-Sun Hong ,  Su Hae Woo ,  Chang Soo Ha

    IPC: G11C16/04 ,  G11C11/4072 ,  G11C11/408 ,  G11C8/04 ,  G11C16/08 ,  G11C16/24 ,  G11C8/18

    Abstract: A semiconductor system may include a memory device and a controller. The memory device may include a plurality of decks. Each of the decks may include word lines and bit lines alternately stacked. The controller may control an operation for data of the decks included in the memory device. The controller may include a counting circuit block for counting access numbers of the word lines and the bit lines. The counting circuit block may include a plurality of x-counting blocks corresponding to the word lines that are stacked a plurality of y-counting blocks corresponding to the bit lines that are stacked. The x-counting blocks may count access numbers of selected word lines in accordance with a selection signal of a corresponding deck among the decks. The y-counting block may count access numbers of selected bit lines in accordance with the selection signal of the corresponding deck.

    System and method for repairing memory
    5.
    发明授权
    System and method for repairing memory 有权

    公开(公告)号：US11538550B2

    公开(公告)日：2022-12-27

    申请号：US16913664

    申请日：2020-06-26

    Applicant: SK hynix Inc.

    Inventor： Hyun Seok Kim ,  Yong Ju Kim ,  Su Hae Woo

    IPC: G06F11/10 ,  G11C29/00 ,  G06F12/02 ,  G06F11/08 ,  G06F11/14

    Abstract: A memory system includes a memory medium and a memory controller. The memory medium has a second address system that is different from a first address system of a host. The memory controller performs a control operation to access the memory medium based on a command from the host. The memory controller is configured to store a second address, corresponding to an address of a read data, when an error of the read data that is outputted from the memory medium is uncorrectable and is configured to repair a region of the memory medium, designated by the second address, when the region of the memory medium that is designated by the second address is repairable.

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