公开(公告)号：US09496878B2

公开(公告)日：2016-11-15

申请号：US13714357

申请日：2012-12-13

Applicant: SK hynix Inc.

Inventor： Hae-Rang Choi ,  Joo-Hwan Cho ,  Kwang-Jin Na ,  Kwan-Dong Kim

IPC: G11C7/22 ,  H03K23/68 ,  H03L7/08 ,  H03K21/00 ,  G11C29/08 ,  H03K21/02 ,  H03L7/099 ,  H03L7/16 ,  H03L7/18 ,  G11C29/02

CPC classification number: H03L7/08 ,  G11C29/023 ,  G11C29/028 ,  G11C29/08 ,  H03K21/00 ,  H03K21/023 ,  H03L7/099 ,  H03L7/16 ,  H03L7/18

Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.

Abstract translation: 锁相环包括相位检测单元，被配置为将反馈时钟的相位与输入时钟的相位进行比较;时钟生成单元，被配置为基于相位的比较结果来调整第一时钟的频率 检测单元，第一分割单元，被配置为通过在测试模式中以第一分频比除以第一时钟而产生输出时钟，并且通过以低于第一分频比的第二分频比除以第一时钟而产生输出时钟 以及第二分割单元，被配置为通过分割输出时钟来产生反馈时钟。