公开(公告)号：US08829960B2

公开(公告)日：2014-09-09

申请号：US13686592

申请日：2012-11-27

Applicant: SK Hynix, Inc.

Inventor： Kwang-Jin Na

IPC: H03L7/06

CPC classification number: H03L7/10 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/0818 ,  H03L7/085 ,  H03L7/087 ,  H03L7/095

Abstract: The DLL comprises a coarse delay line configured to have a plurality of unit delays and delay an reference dock to output a delayed clock, a fine delay line configured to delay the delayed clock to output a delayed output clock, a replica delay unit configured to delay the delayed output clock by an expected modeling value to output a feedback clock, a phase detection unit configured to compare a phase of the feedback clock with a phase of the reference clock to generate first to third phase detection signals based on a result of the comparison, a locking detection unit configured to output a locking signal by selecting a first locking detection signal or a second locking detection signal, and a control unit configured to control the coarse and fine delay lines in response to the locking signal and the first phase detection signal.

Abstract translation: 所述DLL包括粗延迟线，其被配置为具有多个单位延迟并延迟参考基准以输出延迟的时钟;精细延迟线，被配置为延迟所述延迟的时钟以输出延迟的输出时钟;复制延迟单元，被配置为延迟 所述延迟输出时钟由预期建模值输出反馈时钟;相位检测单元，被配置为将所述反馈时钟的相位与所述参考时钟的相位进行比较，以基于所述比较的结果生成第一至第三相位检测信号 锁定检测单元，被配置为通过选择第一锁定检测信号或第二锁定检测信号来输出锁定信号;以及控制单元，被配置为响应于锁定信号和第一相位检测信号来控制粗略和精细延迟线 。

公开(公告)号：US09030907B2

公开(公告)日：2015-05-12

申请号：US14106809

申请日：2013-12-15

Applicant: SK Hynix Inc.

Inventor： Kwang-Jin Na ,  Tae-Wook Kang

IPC: G11C8/00 ,  G11C8/18

CPC classification number: G11C8/18 ,  G11C29/023 ,  G11C29/028

Abstract: A semiconductor device includes a first internal clock generation unit suitable for generating a first internal clock for synchronizing a first signal in response to a first external clock; a second internal clock generation unit suitable for generating a second internal clock for synchronizing a second signal in response to a second external clock; and a delay amount information provision unit suitable for providing delay amount information corresponding to a phase difference between the first internal clock and the second internal clock to an external device.

Abstract translation: 半导体器件包括：第一内部时钟生成单元，适于产生用于响应于第一外部时钟同步第一信号的第一内部时钟; 第二内部时钟生成单元，适于产生用于响应于第二外部时钟同步第二信号的第二内部时钟; 以及延迟量信息提供单元，其适于将对应于第一内部时钟和第二内部时钟之间的相位差的延迟量信息提供给外部设备。

公开(公告)号：US09077438B2

公开(公告)日：2015-07-07

申请号：US14077933

申请日：2013-11-12

Applicant: SK hynix Inc.

Inventor： Tae-Wook Kang ,  Kwang-Jin Na

IPC: H04B3/46

CPC classification number: H04B3/46 ,  H03L7/0812 ,  H03L7/0814

Abstract: A noise detection circuit includes a first delay unit suitable for delaying a periodic wave to output a delayed periodic wave, a first divider unit suitable for dividing the delayed periodic wave to output a first periodic wave, a second divider unit suitable for dividing the periodic wave to output a divided periodic wave, a second delay unit suitable for delaying the divided periodic wave to output a second periodic wave, and a detection unit suitable for comparing the first periodic wave with the second periodic wave and outputting a noise detection signal.

Abstract translation: 噪声检测电路包括适于延迟周期波以输出延迟的周期波的第一延迟单元，适于分割延迟的周期波以输出第一周期波的第一分频器单元，适于分频周期波的第二分频器单元 输出分频周期波，适于延迟分频周期波以输出第二周期波的第二延迟单元，以及适合于将第一周期波与第二周期波进行比较并输出噪声检测信号的检测单元。

公开(公告)号：US09496878B2

公开(公告)日：2016-11-15

申请号：US13714357

申请日：2012-12-13

Applicant: SK hynix Inc.

Inventor： Hae-Rang Choi ,  Joo-Hwan Cho ,  Kwang-Jin Na ,  Kwan-Dong Kim

IPC: G11C7/22 ,  H03K23/68 ,  H03L7/08 ,  H03K21/00 ,  G11C29/08 ,  H03K21/02 ,  H03L7/099 ,  H03L7/16 ,  H03L7/18 ,  G11C29/02

CPC classification number: H03L7/08 ,  G11C29/023 ,  G11C29/028 ,  G11C29/08 ,  H03K21/00 ,  H03K21/023 ,  H03L7/099 ,  H03L7/16 ,  H03L7/18

Abstract: A phase-locked loop includes a phase detection unit configured to compare the phase of a feedback clock with the phase of an input clock, a clock generation unit configured to adjust the frequency of a first clock based on a result of the comparison of the phase detection unit, a first division unit configured to generate an output clock by dividing the first clock at a first division ratio in test mode and generate the output clock by dividing the first clock at a second division ratio that is lower than the first division ratio in normal mode, and a second division unit configured to generate the feedback clock by dividing the output clock.

Abstract translation: 锁相环包括相位检测单元，被配置为将反馈时钟的相位与输入时钟的相位进行比较;时钟生成单元，被配置为基于相位的比较结果来调整第一时钟的频率 检测单元，第一分割单元，被配置为通过在测试模式中以第一分频比除以第一时钟而产生输出时钟，并且通过以低于第一分频比的第二分频比除以第一时钟而产生输出时钟 以及第二分割单元，被配置为通过分割输出时钟来产生反馈时钟。