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    ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME
    1.
    发明申请
    ELECTRONIC DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20210280782A1

    公开(公告)日：2021-09-09

    申请号：US16940060

    申请日：2020-07-27

    Applicant: SK hynix Inc.

    Inventor： Jun Ku AHN

    IPC: H01L45/00

    Abstract: An electronic device including a semiconductor memory is provided. The semiconductor memory includes a plurality of first lines extending in a first direction; a plurality of second lines over the first lines, the second lines extending in a second direction crossing the first direction; a plurality of memory cells disposed at intersection regions of the first lines and the second lines between the first lines and the second lines in a third direction perpendicular to the first and second directions; and a heat sink positioned between two memory cells adjacent to each other in a diagonal direction with respect to the first and second directions.

    SPUTTERING TARGET INCLUDING CARBON-DOPED GST AND METHOD FOR FABRICATING ELECTRONIC DEVICE USING THE SAME
    2.
    发明申请
    SPUTTERING TARGET INCLUDING CARBON-DOPED GST AND METHOD FOR FABRICATING ELECTRONIC DEVICE USING THE SAME 有权

    公开(公告)号：US20220190241A1

    公开(公告)日：2022-06-16

    申请号：US17324833

    申请日：2021-05-19

    Applicant: SK hynix Inc.

    Inventor： Jun Ku AHN

    IPC: H01L45/00 ,  H01L27/24 ,  C23C14/06 ,  C23C14/34

    Abstract: A sputtering target and a method for fabricating an electronic device using the same are provided. A sputtering target may include a carbon-doped GeSbTe alloy, wherein, for the carbon-doped GeSbTe alloy, an average grain diameter of a GeSbTe alloy after sintering is in a range of 0.5 μm to 5 μm, and a first ratio of an average grain diameter of carbon after the sintering is Y (μm) to the average grain diameter of the GeSbTe alloy after the sintering may be in a range of greater than 0.5 and equal to or less than 1.5. Alternatively, for the carbon-doped GeSbTe alloy, a condition of Y=X×(Z/100) may be satisfied, where an average grain diameter of a GeSbTe alloy after sintering is X (μm), an average grain diameter of carbon after the sintering is Y (μm), and a content of carbon is Z (at %).

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220254997A1

    公开(公告)日：2022-08-11

    申请号：US17382057

    申请日：2021-07-21

    Applicant: SK hynix Inc.

    Inventor： Jun Ku AHN ,  Gwang Sun JUNG ,  Jong Ho LEE ,  Uk HWANG

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. The variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area. The variable resistance layer maintains an amorphous state during a program operation.

    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220165791A1

    公开(公告)日：2022-05-26

    申请号：US17234483

    申请日：2021-04-19

    Applicant: SK hynix Inc.

    Inventor： Hyung Keun KIM ,  Jun Ku AHN ,  Jun Young LIM ,  Sung Lae CHO

    IPC: H01L27/24 ,  H01L27/22 ,  H01L43/12 ,  H01L45/00

    Abstract: A semiconductor device includes a stack structure including first electrodes and insulating layers alternately stacked on each other, a second electrode passing through the stack structure, and variable resistance patterns each interposed between the second electrode and a corresponding one of the first electrodes. Each of the first electrodes includes a first sidewall facing the second electrode, and each of the insulating layers includes a second sidewall facing the second electrode. At least a part of each of the variable resistance patterns protrudes farther towards the second electrode than the second sidewall.

    PVD CHAMBER SHIELD STRUCTURE INCLUDING IMPROVED COTAING LAYER OR SHIELD
    7.
    发明申请
    PVD CHAMBER SHIELD STRUCTURE INCLUDING IMPROVED COTAING LAYER OR SHIELD 有权

    公开(公告)号：US20220310372A1

    公开(公告)日：2022-09-29

    申请号：US17474831

    申请日：2021-09-14

    Applicant: SK hynix Inc.

    Inventor： Gwang Sun JUNG ,  Jun Ku AHN ,  Young Ho LEE ,  Jong Ho LEE ,  Uk HWANG

    IPC: H01J37/34 ,  C23C14/34

    Abstract: A PVD chamber shield includes: a shield configured to surround a space between a sputtering target and a substrate that are disposed in a PVD chamber body, the shield having a hollow shape with an inner surface and an outer surface; and a coating layer formed over the inner surface of the shield. The coating layer has i) a dielectric constant not greater than a dielectric constant of a material deposited over the substrate, ii) a porosity greater than 0 vol % and less than 100 vol %, and iii) a thickness greater than 150 pm and less than a given upper limit, the upper limit being set to prevent an occurrence of peeling of a material deposited over the coating layer.

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