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公开(公告)号：US20220320427A1
公开(公告)日：2022-10-06
申请号：US17847034
申请日：2022-06-22
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US20240251687A1
公开(公告)日：2024-07-25
申请号：US18590813
申请日：2024-02-28
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
CPC classification number: H10N70/841 , H10B61/00 , H10B63/84 , H10N50/01 , H10N50/80 , H10N70/011 , H10N70/231
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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Patent Agency Ranking
公开(公告)号：US20210280781A1
公开(公告)日：2021-09-09
申请号：US16984688
申请日：2020-08-04
Applicant: SK hynix Inc.
Inventor： Myoung Sub KIM , Tae Hoon KIM , Beom Seok LEE , Seung Yun LEE , Hwan Jun ZANG , Byung Jick CHO , Ji Sun HAN
Abstract: A method for manufacturing an electronic device including a semiconductor memory may include forming a first carbon electrode material, surface-treating the first carbon electrode material to decrease a surface roughness of the first carbon electrode material, and forming a second carbon electrode material on the treated surface of the first carbon electrode material. The second carbon electrode material may have a thickness that is greater than a thickness of the first carbon electrode material.
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公开(公告)号：US20210013409A1
公开(公告)日：2021-01-14
申请号：US16711286
申请日：2019-12-11
Applicant: SK hynix Inc.
Inventor： Woo Tae LEE , Beom Seok LEE
Abstract: A method of manufacturing an electronic device including a semiconductor memory may include forming a first active layer, forming a first electrode material over the first active layer, performing a heat treatment process on the first electrode material and the first active layer, and forming a second electrode material over the heat-treated first electrode material.
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公开(公告)号：US20220328563A1
公开(公告)日：2022-10-13
申请号：US17494534
申请日：2021-10-05
Applicant: SK hynix Inc.
Inventor： Beom Seok LEE , Won Jun LEE , Seok Man HONG
Abstract: A semiconductor device may include first row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, second row lines each extending in the first direction, a plurality of first memory cells respectively coupled between the first row lines and the column lines, each of the plurality of first memory cells including a first variable resistance layer and a first dielectric layer positioned between the first variable resistance layer and a corresponding one of the first row lines, and a plurality of second memory cells respectively coupled between the second row lines and the column lines, each of the plurality of second memory cells including a second variable resistance layer and a second dielectric layer positioned between the second variable resistance layer and a corresponding one of the second row lines.
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公开(公告)号：US20210083185A1
公开(公告)日：2021-03-18
申请号：US16855760
申请日：2020-04-22
Applicant: SK hynix Inc.
Inventor： Gwang Sun JUNG , Sang Hyun BAN , Jun Ku AHN , Beom Seok LEE , Young Ho LEE , Woo Tae LEE , Jong Ho LEE , Hwan Jun ZANG , Sung Lae CHO , Ye Cheon CHO , Uk HWANG
Abstract: A chalcogenide material may include germanium (Ge), arsenic (As), selenium (Se) and from 0.5 to 10 at % of at least one group 3 element. A variable resistance memory device may include a first electrode, a second electrode, and a chalcogenide film interposed between the first electrode and the second electrode and including from 0.5 to 10 at % of at least one group 3 element. In addition, an electronic device may include a semiconductor memory. The semiconductor memory may include a column line, a row line intersecting the column line, and a memory cell positioned between the column line and the row line, wherein the memory cell comprises a chalcogenide film including germanium (Ge), arsenic (As), selenium (Se), and from 0.5 to 10 at % of at least one group 3 element.
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公开(公告)号：US20210020244A1
公开(公告)日：2021-01-21
申请号：US17039480
申请日：2020-09-30
Applicant: SK hynix Inc.
Inventor： Sang Hyun BAN , Beom Seok LEE , Woo Tae LEE , Tae Hoon KIM , Hwan Jun ZANG , Hye Jung CHOI
IPC: G11C13/00
Abstract: An electronic device includes a semiconductor memory. The semiconductor memory includes a word line, a bit line, and a memory cell coupled to and disposed between the word line and the bit line, the memory cell including a variable resistance layer that remains in an amorphous state regardless of a value of data stored in the memory cell. In a reset operation, the memory cell is programmed to a high-resistance amorphous state by applying, to the memory cell, a sub-threshold voltage that is greater than 0.7 time of a threshold voltage of the memory cell and is smaller than 0.95 time of the threshold voltage.
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