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    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME
    2.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING THE SAME 有权
    半导体存储器件及其操作方法

    公开(公告)号：US20130194870A1

    公开(公告)日：2013-08-01

    申请号：US13750935

    申请日：2013-01-25

    Applicant: SK HYNIX INC. ,  SNU R&DB FOUNDATION

    Inventor： Jong Ho LEE

    IPC: G11C16/26 ,  G11C16/02

    CPC classification number: G11C16/26 ,  G11C16/02 ,  G11C16/0483

    Abstract: A semiconductor memory device includes a memory block including memory strings coupled to and disposed between bit lines and a common source line, and a peripheral circuit configured to perform a read operation of memory cells included in selected memory strings of the memory strings and increase channel potential of unselected memory strings in the read operation.

    Abstract translation: 半导体存储器件包括存储器块，其包括耦合到位线和公共源极线之间并设置在位线和公共源极线之间的存储器串;以及外围电路，被配置为对包含在存储器串的选定存储器串中的存储器单元执行读取操作并增加沟道电位 在读取操作中未选择的内存字符串。

    PVD CHAMBER SHIELD STRUCTURE INCLUDING IMPROVED COTAING LAYER OR SHIELD
    3.
    发明申请
    PVD CHAMBER SHIELD STRUCTURE INCLUDING IMPROVED COTAING LAYER OR SHIELD 有权

    公开(公告)号：US20220310372A1

    公开(公告)日：2022-09-29

    申请号：US17474831

    申请日：2021-09-14

    Applicant: SK hynix Inc.

    Inventor： Gwang Sun JUNG ,  Jun Ku AHN ,  Young Ho LEE ,  Jong Ho LEE ,  Uk HWANG

    IPC: H01J37/34 ,  C23C14/34

    Abstract: A PVD chamber shield includes: a shield configured to surround a space between a sputtering target and a substrate that are disposed in a PVD chamber body, the shield having a hollow shape with an inner surface and an outer surface; and a coating layer formed over the inner surface of the shield. The coating layer has i) a dielectric constant not greater than a dielectric constant of a material deposited over the substrate, ii) a porosity greater than 0 vol % and less than 100 vol %, and iii) a thickness greater than 150 pm and less than a given upper limit, the upper limit being set to prevent an occurrence of peeling of a material deposited over the coating layer.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    6.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20140210058A1

    公开(公告)日：2014-07-31

    申请号：US14166722

    申请日：2014-01-28

    Applicant: SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION ,  SK hynix Inc.

    Inventor： Jong Ho LEE ,  Kyung Do KIM

    IPC: H01L23/48 ,  H01L29/06

    CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/552 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.

    Abstract translation: 一种半导体器件及其制造方法。 该半导体器件包括：在其至少一个主表面上形成有集成电路的具有P型区域的半导体衬底; 插入到半导体衬底的P型区域中的一个或多个通孔电极; 形成在所述半导体衬底和所述通孔电极之间的电介质层; 形成在所述半导体衬底中以与所述电介质层的一部分接触并暴露所述电介质层的其它部分的N型区域; 以及电连接到N型区域并向其施加偏置电压或接地电压的电源电路，使得在通孔电极中流动的电信号在面向暴露部分的半导体衬底的表面上形成反转层 的介电层。

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE
    7.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20220254997A1

    公开(公告)日：2022-08-11

    申请号：US17382057

    申请日：2021-07-21

    Applicant: SK hynix Inc.

    Inventor： Jun Ku AHN ,  Gwang Sun JUNG ,  Jong Ho LEE ,  Uk HWANG

    IPC: H01L45/00 ,  H01L27/24

    Abstract: A semiconductor device may include a first electrode, a second electrode, an insulating layer interposed between the first electrode and the second electrode and including an opening having an inclined sidewall, a variable resistance layer formed in the opening, and a liner interposed between the variable resistance layer and the insulating layer and between the variable resistance layer and the first electrode. The variable resistance layer includes a first surface and a second surface, the first surface facing the first electrode and having a first area, the second surface facing the second electrode and having a second area different from the first area. The variable resistance layer maintains an amorphous state during a program operation.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20150270167A1

    公开(公告)日：2015-09-24

    申请号：US14732530

    申请日：2015-06-05

    Applicant: SK hynix Inc. ,  SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION

    Inventor： Jong Ho LEE ,  Kyung Do KIM

    IPC: H01L21/768 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

    CPC classification number: H01L21/76877 ,  H01L21/02164 ,  H01L21/265 ,  H01L21/324 ,  H01L21/76831 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/552 ,  H01L24/16 ,  H01L25/0657 ,  H01L2223/6622 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2225/06541 ,  H01L2924/12036 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/00

    Abstract: A semiconductor device and a method of fabricating the same. The semiconductor device includes a semiconductor substrate having a P-type region, on at least one main surface of which integrated circuits are formed; one or more via electrodes inserted into the P-type region of the semiconductor substrate; a dielectric layer formed between the semiconductor substrate and the via electrodes; an N-type region, which is formed in the semiconductor substrate to contact a portion of the dielectric layer and to expose other portion of the dielectric layer; and a power circuit, which is electrically connected to the N-type region and apply a bias voltage or a ground voltage thereto, such that electric signals flowing in the via electrodes form an inversion layer on a surface of the semiconductor substrate facing the exposed portion of the dielectric layer.

    Abstract translation: 一种半导体器件及其制造方法。 该半导体器件包括：在其至少一个主表面上形成有集成电路的具有P型区域的半导体衬底; 插入到半导体衬底的P型区域中的一个或多个通孔电极; 形成在所述半导体衬底和所述通孔电极之间的电介质层; 形成在所述半导体衬底中以与所述电介质层的一部分接触并暴露所述电介质层的其它部分的N型区域; 以及电连接到N型区域并向其施加偏置电压或接地电压的电源电路，使得在通孔电极中流动的电信号在面向暴露部分的半导体衬底的表面上形成反转层 的介电层。

    DATA STORAGE DEVICE AND METHOD OF DRIVING THE SAME
    10.
    发明申请
    DATA STORAGE DEVICE AND METHOD OF DRIVING THE SAME 有权
    数据存储装置及其驱动方法

    公开(公告)号：US20160260490A1

    公开(公告)日：2016-09-08

    申请号：US15063060

    申请日：2016-03-07

    Applicant: SK hynix Inc. ,  Seoul National University R&DB Foundation

    Inventor： Jong Ho LEE ,  Ho Jung KANG ,  Nag Yong CHOI ,  Byeong Il HAN ,  Kyoung Jin PARK ,  Sung Yong CHUNG

    IPC: G11C16/16 ,  H01L27/115

    CPC classification number: G11C16/16 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/3472 ,  H01L27/1157 ,  H01L27/11582 ,  H01L29/792

    Abstract: A data storage device includes a non-volatile memory device, which includes a memory cell array including a plurality of memory cells and a control circuit. Each of the memory cells includes a channel layer, a charge trap layer on the channel layer, and a control electrode on the charge trap layer, the charge trap layer being shared by the memory cells. The charge trap layer includes program regions respectively disposed below the control electrodes of the memory cells, and charge spread blocking regions, each of which is disposed between two adjacent ones of the program regions and between two adjacent ones of the control electrodes. The control circuit controls the memory cell array so that a potential barrier is generated in the charge spread blocking regions by charging the charge spread blocking regions with charges having the same polarity as that of program charges stored in the program regions.

    Abstract translation: 数据存储装置包括非易失性存储装置，其包括包括多个存储单元的存储单元阵列和控制电路。 每个存储单元包括沟道层，沟道层上的电荷陷阱层和电荷陷阱层上的控制电极，电荷陷阱层由存储单元共享。 电荷陷阱层包括分别设置在存储单元的控制电极下方的编程区域和电荷扩展阻挡区域，每个区域设置在两个相邻的编程区域之间和两个相邻的控制电极之间。 控制电路控制存储单元阵列，从而通过以与存储在程序区域中的程序电荷具有相同极性的电荷充电电荷扩展阻挡区域，在电荷扩展阻挡区域中产生势垒。

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