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公开(公告)号：US20240312523A1
公开(公告)日：2024-09-19
申请号：US18464058
申请日：2023-09-08
申请人： SK hynix Inc.
发明人： Sung Hyun HWANG , Jae Yeop JUNG , Se Chun PARK
CPC分类号： G11C16/10 , G11C16/0483 , G11C2216/02
摘要： A memory device applies voltage to drain select lines, which are determined individually. A program operation control unit applies a precharge voltage to a drain select line coupled to a cell string selected from the first cell string and the second cell string before a program voltage is applied to the word line, during a time determined depending on a resistance value of the drain select line coupled to the selected cell string.
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公开(公告)号：US20230393759A1
公开(公告)日：2023-12-07
申请号：US17968083
申请日：2022-10-18
申请人： SK hynix Inc.
发明人： Chan Hui JEONG , Hyung Jin CHOI , Se Chun PARK
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0679
摘要： A memory device, and a method of operating the same, includes a plurality of memory cells coupled to a plurality of word lines, a peripheral circuit configured to perform a program operation of storing data in the plurality of memory cells, a weak word line information storage configured to store information about a weak word line among the plurality of word lines, and a program operation controller configured to control the peripheral circuit such that the program operation is performed in a first program mode or a second program mode depending on a result of determining whether a selected word line corresponding to an address provided from a memory controller is a weak word line by comparing word lines based on the information about the weak word line.
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公开(公告)号：US20240265980A1
公开(公告)日：2024-08-08
申请号：US18359904
申请日：2023-07-27
申请人： SK hynix Inc.
发明人： Yeong Jo MUN , Dong Hun KWAK , Se Chun PARK
CPC分类号： G11C16/3427 , G11C11/5628 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/3459
摘要： A memory device includes: a memory block including a plurality of memory cells; a peripheral circuit for performing a program operation on selected memory cells among the plurality of memory cells; and a control logic for controlling the program operation of the peripheral circuit. The control logic controls the peripheral circuit to perform a foggy program operation on first memory cells connected to a first word line among the plurality of memory cells, perform a foggy program operation on second memory cells connected to a second word line adjacent to the first word line among the plurality of memory cells, and perform a fine program operation on the first memory cells, based on a target program state of the second memory cells.
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公开(公告)号：US20240176503A1
公开(公告)日：2024-05-30
申请号：US18312459
申请日：2023-05-04
申请人： SK hynix Inc.
发明人： Hyung Jin CHOI , Gwi Han KO , Chan Hui JEONG , Se Chun PARK
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0659 , G06F3/0679
摘要： A memory device includes: a plurality of memory cells; a peripheral circuit configured to perform a plurality of program loops each including a program voltage apply operation of applying a program voltage to selected memory cells, and a verify operation of verifying a program state of the selected memory cells; and a control logic configured to control the peripheral circuit to apply program voltages increasing in a step-wise manner by a first step voltage in program loops in a first state, and increasing by a second step voltage that is lower than the first step voltage in program loops in a second state that occur after the program loops in the first state. The first state and the second state of the program loops are determined based on when a verify operation on a program state having a highest threshold voltage is performed.
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公开(公告)号：US20240020022A1
公开(公告)日：2024-01-18
申请号：US18073130
申请日：2022-12-01
申请人： SK hynix Inc.
发明人： Chan Hui JEONG , Dong Hun KWAK , Se Chun PARK
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0629 , G06F3/0679
摘要： A memory device includes a precharge time information storage for storing information on a first precharge time for which a bit line control signal is applied and a second precharge time for which a source line control signal is applied, which are determined according to a degree to which a program operation is performed. The memory device also includes a precharge voltage controller for providing the bit line control signal and the source line control signal respectively to page buffers and a source line driver for a longer precharge time selected from the first precharge time and the second precharge time in the program operation.
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公开(公告)号：US20230395169A1
公开(公告)日：2023-12-07
申请号：US17970079
申请日：2022-10-20
申请人： SK hynix Inc.
发明人： Jong Hoon LEE , Se Chun PARK
CPC分类号： G11C16/3459 , G11C16/102 , G11C16/24 , G11C16/3404
摘要： Provided herein may be a memory device and a method of operating the same. The memory device may include a plurality of memory cells, a peripheral circuit configured to perform a verify operation that identifies threshold voltages of the plurality of memory cells by using a first verify voltage and a second verify voltage, and a program operation controller configured to control the peripheral circuit, after the verify operation is terminated and during a period in which a program voltage is applied to the plurality of memory cells, to apply a first control signal to a page buffer that is coupled to a first memory cell having a threshold voltage that is higher than the first verify voltage and lower than the second verify voltage, and apply a second control signal having a lower level voltage than the first control signal to the page buffer.
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公开(公告)号：US20220180931A1
公开(公告)日：2022-06-09
申请号：US17350637
申请日：2021-06-17
申请人： SK hynix Inc.
发明人： Sung Bak KIM , Kyu Nam LIM , Se Chun PARK
摘要： The present technology relates to a semiconductor memory device and a method of operating the same. The semiconductor memory device includes a memory cell array including a plurality of memory blocks, peripheral circuits for performing a program operation on a selected memory block among the plurality of memory blocks, and a control logic for controlling the peripheral circuits to perform a detrap operation between a program voltage apply operation and a program verify operation during the program operation, and the peripheral circuits apply a positive set voltage to a source line connected to the selected memory block during the detrap operation.
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公开(公告)号：US20240304249A1
公开(公告)日：2024-09-12
申请号：US18352963
申请日：2023-07-14
申请人： SK hynix Inc.
发明人： Hyung Jin CHOI , Se Chun PARK , Chan Hui JEONG
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459
摘要： A memory device may include memory cells connected to a selected word line, and a peripheral circuit configured to store information regarding a foggy program pass loop in which a target program state is determined as foggy program pass during a foggy program operation on the selected word line, calculate a fine program pass loop based on the foggy program pass loop, and determine the target program state as fine program pass in the fine program pass loop of a fine program operation on the selected word line.
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公开(公告)号：US20240185939A1
公开(公告)日：2024-06-06
申请号：US18325999
申请日：2023-05-31
申请人： SK hynix Inc.
发明人： Se Chun PARK
IPC分类号： G11C29/12
CPC分类号： G11C29/12005 , G11C2029/1204
摘要： The present technology relates to an electronic device. According to the present technology, a memory device may include a plurality of memory cells, a defect detector, and a test controller. The defect detector may generate defect information indicating a defect state in which a value of a cell current measured in a sensing operation on selected memory cells among the plurality of memory cells is less than a threshold value. The test controller may count fail bits from a result of a test operation performed on the selected memory cells using a test reference current in response to the defect information, and set a bit line voltage to be used in the sensing operation based on a comparison result between a number of fail bits detected in the test operation and a reference number.
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公开(公告)号：US20220189567A1
公开(公告)日：2022-06-16
申请号：US17354169
申请日：2021-06-22
申请人： SK hynix Inc.
发明人： Jong Hoon LEE , Se Chun PARK
摘要： The memory device may include a plurality of memory cells, a peripheral circuit, and a control logic. The peripheral circuit may perform a program operation on the plurality of memory cells and may perform program verify operations each including at least one verify loop corresponding to a plurality of program states programmed in the program operation. The control logic may control the peripheral circuit to perform a verify pulse apply operation and an additional verify pulse apply operation when a target verify loop count exceeds a reference count corresponding to the target program state, and may determine a failure of the program verify operation corresponding to the target program state based on results of the verify pulse apply operation and the additional verify pulse apply operation. A verify voltage of the additional verify pulse apply operation is higher than a verify voltage of the verify pulse apply operation.
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