公开(公告)号：US11482283B2

公开(公告)日：2022-10-25

申请号：US17214592

申请日：2021-03-26

Applicant: SK hynix Inc.

Inventor： Ki Won Lee ,  Seok Man Hong ,  Tae Hoon Kim ,  Hyung Dong Lee

IPC: G11C11/56 ,  G11C13/00

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.

公开(公告)号：US11864394B2

公开(公告)日：2024-01-02

申请号：US17494534

申请日：2021-10-05

Applicant: SK hynix Inc.

Inventor： Beom Seok Lee ,  Won Jun Lee ,  Seok Man Hong

IPC: G11C11/00 ,  H10B63/00 ,  G11C13/00 ,  H10N70/20

CPC classification number: H10B63/84 ,  G11C13/004 ,  G11C13/0004 ,  G11C13/0069 ,  H10N70/231 ,  G11C2213/71

Abstract: A semiconductor device may include first row lines each extending in a first direction, column lines each extending in a second direction crossing the first direction, second row lines each extending in the first direction, a plurality of first memory cells respectively coupled between the first row lines and the column lines, each of the plurality of first memory cells including a first variable resistance layer and a first dielectric layer positioned between the first variable resistance layer and a corresponding one of the first row lines, and a plurality of second memory cells respectively coupled between the second row lines and the column lines, each of the plurality of second memory cells including a second variable resistance layer and a second dielectric layer positioned between the second variable resistance layer and a corresponding one of the second row lines.

公开(公告)号：US20230413699A1

公开(公告)日：2023-12-21

申请号：US18061374

申请日：2022-12-02

Applicant: SK hynix Inc.

Inventor： Hye Jung Choi ,  Jae hyuk Park ,  Seok Man Hong

IPC: H10N70/00 ,  H10B63/00

CPC classification number: H01L45/149 ,  H01L45/1253 ,  H01L45/1641 ,  H01L45/145 ,  H01L27/2481 ,  H01L45/1675

Abstract: A semiconductor device may include: a substrate including a peripheral circuit region and a cell region having a first cell region and a second cell region, the second cell region being farther from the peripheral circuit region than the first cell region; a plurality of memory cells disposed at intersection regions between first conductive lines and second conductive lines, respectively, the memory cells including a first memory cell disposed in the first cell region and a second memory cell disposed in the second cell region, wherein a first electrode layer of the first memory cell and a second electrode layer of the second memory cell include a conductive material, and wherein the first electrode layer further includes a first dopant that increases a resistivity of the conductive material.

公开(公告)号：US10964382B2

公开(公告)日：2021-03-30

申请号：US16296796

申请日：2019-03-08

Applicant: SK hynix Inc.

Inventor： Ki Won Lee ,  Seok Man Hong ,  Tae Hoon Kim ,  Hyung Dong Lee

IPC: G11C13/00

Abstract: A variable resistive memory device includes a memory cell, a first circuit, and a second circuit. The memory cell is connected between a word line and a bit line. The first circuit provides the bit line with a first pulse voltage based on at least one enable signal. The second circuit provides the word line with a second pulse voltage based on the enable signal. The first circuit generates the first pulse voltage increased in steps from an initial voltage level to a target voltage level.