公开(公告)号：US20230238065A1

公开(公告)日：2023-07-27

申请号：US17871251

申请日：2022-07-22

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/26

CPC分类号： G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26

摘要： A memory device may include a plurality of memory cells, a peripheral circuit configured to perform a plurality of program loops on selected memory cells among the plurality of memory cells, each of the plurality of program loops including a program pulse application operation and a program verify operation, and control logic configured to control the peripheral circuit to suspend an nth program loop (n is a natural number equal to or greater than 1) among the plurality of program loops in response to a suspend command received during the nth program loop, and to resume the nth program loop with a negative verify operation in response to a resume command. The negative verify operation applies a negative voltage having a voltage less than a state voltage at the time of application of the resume command.

公开(公告)号：US20220230693A1

公开(公告)日：2022-07-21

申请号：US17369393

申请日：2021-07-07

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI

IPC分类号： G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30

摘要： Provided herein is a memory device and a method of operating the same. The memory device may include a memory block including a plurality of memory cells, and a peripheral circuit configured to apply a plurality of operating voltages to a plurality of word lines of the memory block during a program operation, wherein, during a verify operation included in the program operation, the peripheral circuit may be configured to allow a selected word line, among the plurality of word lines, to float, and may decrease a potential of the selected word line to a pre-level by decreasing potentials of adjacent word lines to the selected word line.

公开(公告)号：US20230162806A1

公开(公告)日：2023-05-25

申请号：US17730917

申请日：2022-04-27

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI ,  Jin Haeng Lee

IPC分类号： G11C16/34 ,  G11C16/24

CPC分类号： G11C16/3427 ,  G11C16/24

摘要： A memory device includes a memory structure and a control circuit. The memory structure includes plural page buffers coupled to non-volatile memory cells. Each non-volatile memory cell is capable of storing data. The plural page buffers are disposed in a predetermined direction. The control circuit is configured to separate reset sections of two page buffers from each other by a time corresponding to at least one of the reset sections. The two page buffers are disposed adjacent to each other among the plural page buffers.

公开(公告)号：US20220328114A1

公开(公告)日：2022-10-13

申请号：US17487705

申请日：2021-09-28

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI ,  Jong Woo KIM

IPC分类号： G11C16/34 ,  G11C16/24 ,  G11C16/10 ,  G11C16/26 ,  G11C7/10

摘要： A page buffer includes a bit line controller connected between a bit line and a sensing node, wherein the bit line controller is capable of adjusting a potential level of the sensing node, based on a cell current amount of the bit line, by performing an evaluation operation. The page buffer also includes a first latch unit connected to the sensing node, wherein the first latch unit is capable of adjusting an operation period of the evaluation operation. The page buffer further includes a second latch unit for latching verify data, based on the potential level of the sensing node.

公开(公告)号：US20240038312A1

公开(公告)日：2024-02-01

申请号：US18073751

申请日：2022-12-02

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI

IPC分类号： G11C16/34 ,  G11C16/24 ,  G11C16/08 ,  G11C16/10

CPC分类号： G11C16/3459 ,  G11C16/24 ,  G11C16/08 ,  G11C16/102

摘要： A memory device includes: a plurality of page buffers connected a plurality of bit lines and configured to selectively precharge the bit lines, and a control circuit configured to: perform a first verify operation by applying a precharge voltage to a first bit line among the bit lines according to program data and by applying a first verify voltage to a selected word line, perform a second verify operation, after the first verify operation, by applying the precharge voltage to a second bit line not overlapping the first bit line and by applying a second verify voltage to the selected word line, and perform at least one of an operation of floating the first bit line and an operation of applying the precharge voltage according to a threshold voltage of a memory cell connected to the first bit line during the second verify operation.

公开(公告)号：US20220328107A1

公开(公告)日：2022-10-13

申请号：US17481927

申请日：2021-09-22

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI

IPC分类号： G11C16/26

摘要： The present technology provides a method of operating a semiconductor memory device detecting a threshold voltage distribution for memory cells included in a page selected from among a plurality of memory cells. The method of operating the semiconductor memory device includes selecting a target state in which the threshold voltage distribution is to be detected, determining a plurality of read voltages for dividing a voltage range in which a threshold voltage of the selected target state is distributed, and performing a plurality of sensing operations using the plurality of read voltages on the selected page. Masking to the target state is applied in each of the plurality of sensing operations.

公开(公告)号：US20210183447A1

公开(公告)日：2021-06-17

申请号：US16890574

申请日：2020-06-02

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/30 ,  G11C16/26

摘要： The present disclosure relates to a memory device. The memory device includes first memory cell strings, second memory cell strings, a peripheral circuit, and a control logic. The peripheral circuit is connected to first drain select transistors of each of the first memory cell strings through first bit lines, and is connected to second drain select transistors of each of the second memory cell strings through second bit lines. The control logic controls the peripheral circuit to increase a potential of a program inhibit bit line among the first bit lines to a first voltage, and float the program inhibit bit line and increase a potential of the second bit line to a second voltage after the potential of the program inhibit bit line increases to the first voltage.

公开(公告)号：US20220262411A1

公开(公告)日：2022-08-18

申请号：US17395352

申请日：2021-08-05

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI

IPC分类号： G11C7/10 ,  G11C7/12 ,  G11C7/14

摘要： The present technology includes a memory device. The memory device includes memory cells, page buffers configured to store sensed data obtained from the memory cells, a current sensing circuit configured to compare a sensed voltage generated according to the sensed data and a reference voltage generated according to an allowable fail bit code, and output a pass signal or a fail signal according to a comparison result, and a fail bit manager configured to increase an allowable number of fail bits included in the allowable fail bit code until the pass signal is output from the current sensing circuit, change the allowable fail bit code according to the allowable number of fail bits, and provide the allowable fail bit code to the current sensing circuit.

公开(公告)号：US20210295927A1

公开(公告)日：2021-09-23

申请号：US16990805

申请日：2020-08-11

申请人： SK hynix Inc.

发明人： Kang Woo PARK ,  Soo Yeol CHAI

IPC分类号： G11C16/24 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26 ,  G11C16/34

摘要： The present technology relates to a page buffer and a semiconductor memory device including the page buffer. The page buffer includes a first latch circuit configured to store data corresponding to one of a first program state and a second program state, a bit line controller connected to a bit line of a memory block and precharging the bit line by applying one of a first set voltage and a second set voltage to the bit line according to the data stored in the first latch circuit during a bit line precharge operation in a program verify operation, and a second latch circuit connected to the bit line controller through a main sensing node and configured to sense first verify data according to a potential level of the main sensing node during the program verify operation.

公开(公告)号：US20210295918A1

公开(公告)日：2021-09-23

申请号：US16989169

申请日：2020-08-10

申请人： SK hynix Inc.

发明人： Soo Yeol CHAI

IPC分类号： G11C16/10 ,  G11C16/34

摘要： Provided herein may be a memory device and a method of operating the same. The memory device may include a memory cell array including a plurality of memory cells, a peripheral circuit configured to program the plurality of memory cells to a plurality of program states, and a control logic configured to control the peripheral circuit so that program operations corresponding to the plurality of program states are performed, wherein the control logic controls the peripheral circuit so that, during a program operation for a target program state, among the plurality of program states, memory cells to be programmed to an immediately higher program state than the target program state are programmed to the target program state.