公开(公告)号：US20210043248A1

公开(公告)日：2021-02-11

申请号：US16858468

申请日：2020-04-24

申请人： SK hynix Inc. ,  Seoul National University R&DB Foundation

发明人： Eojin LEE ,  Ingab KANG ,  Jung Ho AHN

IPC分类号： G11C11/406 ,  G11C11/4076 ,  G11C11/4072 ,  G11C11/408 ,  G11C11/409

摘要： A row hammer prevention circuit for providing a reference address to perform an additional refresh operation includes a history storage circuit configured to store one or more first addresses, each of the first addresses having been provided as the reference address. The row hammer prevention circuit further includes an address storage circuit configured to store a row address corresponding to an active command, a reference address storage circuit configured to store one or more second addresses, and a control circuit configured to provide the reference address in response to a refresh command.

公开(公告)号：US20210398597A1

公开(公告)日：2021-12-23

申请号：US17462298

申请日：2021-08-31

申请人： Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

发明人： Seungwoo SEO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC分类号： G11C16/30 ,  G06N3/02 ,  G11C5/02 ,  G11C16/10

摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.

公开(公告)号：US20210117761A1

公开(公告)日：2021-04-22

申请号：US16857740

申请日：2020-04-24

申请人： Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

发明人： Yuhwan Ro ,  Byeongho KIM ,  Jaehyun Park ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewon CHOI

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F9/30 ,  G06F9/38 ,  G06F17/16

摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

公开(公告)号：US20220374693A1

公开(公告)日：2022-11-24

申请号：US17876136

申请日：2022-07-28

申请人： Samsung Electronics Co., Ltd ,  Seoul National University R&DB Foundation

发明人： Yuhwan RO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC分类号： G06N3/063 ,  G06N3/08 ,  G06N20/10 ,  G06F17/16 ,  G06F9/38 ,  G06F9/30

摘要： A processor-implemented data processing method includes: generating compressed data of first matrix data based on information of a distance between valid elements included in the first matrix data; fetching second matrix data based on the compressed data; and generating output matrix data based on the compressed data and the second matrix data.

公开(公告)号：US20210110876A1

公开(公告)日：2021-04-15

申请号：US16833864

申请日：2020-03-30

申请人： Samsung Electronics Co., Ltd. ,  Seoul National University R&DB Foundation

发明人： Seungwoo SEO ,  Byeongho KIM ,  Jaehyun PARK ,  Jungho AHN ,  Minbok WI ,  Sunjung LEE ,  Eojin LEE ,  Wonkyung JUNG ,  Jongwook CHUNG ,  Jaewan CHOI

IPC分类号： G11C16/30 ,  G11C5/02 ,  G11C16/10 ,  G06N3/02

摘要： A semiconductor memory device includes a plurality of memory banks including a first memory bank group including a computation circuit and a second memory bank group without a computation circuit; and a control circuit configured to control a PIM operation by the first memory bank group to be performed together with processing of memory requests for the plurality of memory banks while satisfying a maximum power consumption condition of the semiconductor memory device.