公开(公告)号：US11063035B2

公开(公告)日：2021-07-13

申请号：US16803748

申请日：2020-02-27

Applicant: SOCIONEXT INC.

Inventor： Chika Ito ,  Isaya Sobue ,  Hidetoshi Tanaka

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: An ESD protection circuit includes a first fin structure having fins of a first conductivity type and a second fin structure having fins of a second conductivity type, the second fin structure being opposed to the first fin structure. A first power interconnect connected with the first fin structure and a signal interconnect connected with the second fin structure are formed in a first interconnect layer, and a second power interconnect connected with the first power interconnect is formed in a second interconnect layer. The width occupied by the second fin structure is greater than that of the first fin structure, and the width of the signal interconnect is greater than that of the first power interconnect.

公开(公告)号：US10886220B2

公开(公告)日：2021-01-05

申请号：US16555890

申请日：2019-08-29

Applicant: Socionext Inc.

Inventor： Chika Ito ,  Isaya Sobue

IPC: H01L23/528 ,  H01L27/04 ,  H03K19/17736 ,  H01L27/02

Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.