公开(公告)号：US11295987B2

公开(公告)日：2022-04-05

申请号：US16905136

申请日：2020-06-18

Applicant: SOCIONEXT INC.

Inventor： Isaya Sobue

IPC: H01L27/02 ,  H01L21/8234 ,  H01L21/02 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  B82Y10/00

Abstract: A layout structure of an output circuit using vertical nanowire (VNW) FETs is provided. The output circuit includes a transistor of a first conductivity type provided between a power supply and an output signal line and configured to receive an output control signal at its gate. The transistor includes a plurality of VNW FETs placed in an array in the X and Y directions, and the plurality of VNW FETs have tops connected to the output signal line, bottoms to which a power supply voltage is supplied, and gates to which the output control signal is supplied.

公开(公告)号：US11955508B2

公开(公告)日：2024-04-09

申请号：US17546463

申请日：2021-12-09

Applicant: Socionext Inc.

Inventor： Isaya Sobue ,  Hideyuki Komuro

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/528 ,  H01L27/092

CPC classification number: H01L28/20 ,  H01L27/0629 ,  H01L23/5286 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

公开(公告)号：US11699660B2

公开(公告)日：2023-07-11

申请号：US17180094

申请日：2021-02-19

Applicant: SOCIONEXT INC.

Inventor： Isaya Sobue ,  Hidetoshi Tanaka ,  Mai Tsukamoto

IPC: H01L23/528 ,  H01L27/02

CPC classification number: H01L23/5286 ,  H01L27/0292

Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

公开(公告)号：US11063035B2

公开(公告)日：2021-07-13

申请号：US16803748

申请日：2020-02-27

Applicant: SOCIONEXT INC.

Inventor： Chika Ito ,  Isaya Sobue ,  Hidetoshi Tanaka

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: An ESD protection circuit includes a first fin structure having fins of a first conductivity type and a second fin structure having fins of a second conductivity type, the second fin structure being opposed to the first fin structure. A first power interconnect connected with the first fin structure and a signal interconnect connected with the second fin structure are formed in a first interconnect layer, and a second power interconnect connected with the first power interconnect is formed in a second interconnect layer. The width occupied by the second fin structure is greater than that of the first fin structure, and the width of the signal interconnect is greater than that of the first power interconnect.

公开(公告)号：US12191345B2

公开(公告)日：2025-01-07

申请号：US18598870

申请日：2024-03-07

Applicant: Socionext Inc.

Inventor： Isaya Sobue ,  Hideyuki Komuro

IPC: H01L21/00 ,  H01L27/06 ,  H01L49/02 ,  H01L23/528 ,  H01L27/092

Abstract: A semiconductor device includes a substrate; a first semiconductor region formed over the substrate; a second semiconductor region formed over the substrate, and electrically connected to the first semiconductor region; a third semiconductor region formed over the substrate, and positioned between the first semiconductor region and the second semiconductor region; a fourth semiconductor region formed over the first semiconductor region; a fifth semiconductor region formed over the second semiconductor region, and electrically connected to the fourth semiconductor region; a sixth semiconductor region formed over the third semiconductor region, and positioned between the fourth semiconductor region and the fifth semiconductor region; and wires formed between the first semiconductor region and the second semiconductor region, and between the fourth semiconductor region and the fifth semiconductor region, to cover the third semiconductor region and the sixth semiconductor region, the wires including conductors.

公开(公告)号：US11152346B2

公开(公告)日：2021-10-19

申请号：US17093400

申请日：2020-11-09

Applicant: Socionext Inc.

Inventor： Isaya Sobue

IPC: H01L27/01

Abstract: A capacitive element using VNW FETs is provided. First and second components each constituting a transistor are arranged in an X direction. From the first component, a first gate interconnect extends away from the second component, and a first top interconnect and a first bottom interconnect extend toward the second component. From the second component, a second gate interconnect extends toward the first component, and a second top interconnect and a second bottom interconnect extend away from the first component. The first top interconnect, the first bottom interconnect, and the second gate interconnect are connected.

公开(公告)号：US10886220B2

公开(公告)日：2021-01-05

申请号：US16555890

申请日：2019-08-29

Applicant: Socionext Inc.

Inventor： Chika Ito ,  Isaya Sobue

IPC: H01L23/528 ,  H01L27/04 ,  H03K19/17736 ,  H01L27/02

Abstract: For a semiconductor integrated circuit device in which IO cells are disposed, power supply voltage drop can be reduced using a multilayer interconnect. A power supply interconnect formed in a plurality of interconnect layers extends in an X direction that is a same direction as a direction in which the IO cells are aligned. In an area of a power supply IO cell, a power supply interconnect extending in a Y direction is disposed in one of the interconnect layers in which the power supply interconnect is not formed and an interconnect piece is disposed in a same position as a position of the power supply interconnect formed in an area of a signal IO cell in the Y direction at each of both ends of the area of the power supply IO cell in the X direction.

公开(公告)号：US12159866B2

公开(公告)日：2024-12-03

申请号：US17394065

申请日：2021-08-04

Applicant: SOCIONEXT INC.

Inventor： Isaya Sobue

IPC: H01L27/06 ,  B82Y10/00 ,  H01L21/822 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786

Abstract: A layout structure of a capacitive element using a complementary FET (CFET) and having a high breakdown voltage is provided. In the capacitive element, first and second transistors overlap as viewed in plan, and the gates thereof are mutually connected. Third and fourth transistors overlap as viewed in plan, and the gates thereof are mutually connected. Nodes of the first and third transistors are mutually connected through a local interconnect, and nodes of the second and fourth transistors are mutually connected through a local interconnect.

公开(公告)号：US11557610B2

公开(公告)日：2023-01-17

申请号：US17385451

申请日：2021-07-26

Applicant: SOCIONEXT INC.

Inventor： Isaya Sobue

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.

公开(公告)号：US11101292B2

公开(公告)日：2021-08-24

申请号：US16684322

申请日：2019-11-14

Applicant: SOCIONEXT INC.

Inventor： Isaya Sobue

IPC: H01L27/118 ,  H01L27/02

Abstract: A semiconductor integrated circuit device including a plurality of rows of IO cells has a configuration capable of avoiding a latchup error without causing an increase in area. The device includes a first IO cell row placed closest to an edge of a chip and a second IO cell row placed adjacent to a core region side of the first IO cell row. Each of the IO cells of the first and second IO cell rows has a high power supply voltage region and a low power supply voltage region provided separately in a direction perpendicular to a direction in which the IO cells are lined up. The IO cell rows are placed so that the high power supply voltage regions of these rows are mutually opposed.