公开(公告)号：US11699660B2

公开(公告)日：2023-07-11

申请号：US17180094

申请日：2021-02-19

Applicant: SOCIONEXT INC.

Inventor： Isaya Sobue ,  Hidetoshi Tanaka ,  Mai Tsukamoto

IPC: H01L23/528 ,  H01L27/02

CPC classification number: H01L23/5286 ,  H01L27/0292

Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

公开(公告)号：US11063035B2

公开(公告)日：2021-07-13

申请号：US16803748

申请日：2020-02-27

Applicant: SOCIONEXT INC.

Inventor： Chika Ito ,  Isaya Sobue ,  Hidetoshi Tanaka

IPC: H01L27/02 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/06

Abstract: An ESD protection circuit includes a first fin structure having fins of a first conductivity type and a second fin structure having fins of a second conductivity type, the second fin structure being opposed to the first fin structure. A first power interconnect connected with the first fin structure and a signal interconnect connected with the second fin structure are formed in a first interconnect layer, and a second power interconnect connected with the first power interconnect is formed in a second interconnect layer. The width occupied by the second fin structure is greater than that of the first fin structure, and the width of the signal interconnect is greater than that of the first power interconnect.

公开(公告)号：US11444079B2

公开(公告)日：2022-09-13

申请号：US17002392

申请日：2020-08-25

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi Tanaka

IPC: H01L27/088 ,  H01L29/78 ,  H01L23/535 ,  H01L29/06

Abstract: A semiconductor device includes: a semiconductor substrate; a VNW transistor being a functional element provided with a first projection formed on the semiconductor substrate, having a semiconductor material, and having a lower end and an upper end; a dummy functional element provided with a second projection formed on the semiconductor substrate, having a semiconductor material, having a lower end and an upper end, and arranged side by side with the first projection; and a first wiring formed above the first projection and above the second projection, electrically connected to the upper end of the first projection, and electrically isolated from the upper end of the second projection. Consequently, the semiconductor device capable of suppressing variation in characteristics of the VNW transistors is realized.

公开(公告)号：US20200381416A1

公开(公告)日：2020-12-03

申请号：US16999933

申请日：2020-08-21

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi Tanaka

IPC: H01L27/02 ,  H01L29/06

Abstract: An ESD protection diode in a semiconductor device includes: a semiconductor substrate; a diode group that has a plurality of grouped VNW diodes, each of the VNW diodes having a VNW having a lower end and an upper end, that are formed on the semiconductor substrate and have a semiconductor material; and a top plate that is formed above the diode group and is a conductive layer electrically connected to the upper ends of the VNWs of the respective VNW diodes, and there is fabricated the semiconductor device that is capable of, even when large current flows through the VNW diode, suppressing current concentration and preventing damage of the VNW diode.

公开(公告)号：US10854710B2

公开(公告)日：2020-12-01

申请号：US16563670

申请日：2019-09-06

Applicant: SOCIONEXT, INC.

Inventor： Hidetoshi Tanaka

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L29/775

Abstract: A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.

公开(公告)号：US10461150B2

公开(公告)日：2019-10-29

申请号：US15972949

申请日：2018-05-07

Applicant: SOCIONEXT, INC.

Inventor： Hidetoshi Tanaka

IPC: H01L29/06 ,  H01L27/088 ,  H01L27/02 ,  H01L29/775

Abstract: A semiconductor device includes a first transistor formed on a substrate and including first and second impurity regions, a second transistor formed on the substrate and including a third impurity region electrically connected to the second impurity region, and a fourth impurity region, a power supply terminal electrically connected to the first impurity region, a ground terminal electrically connected to the fourth impurity region, a first guard ring surrounding the first transistor in a plan view and electrically connected to the ground terminal, and a second guard ring surrounding the second transistor in a plan view and electrically connected to the ground terminal. A conductivity type of the first through fourth impurity regions is different from a conductivity type of the first and second guard rings. The second guard ring has a width narrower than a width of the first guard ring in a plan view.

公开(公告)号：US11824055B2

公开(公告)日：2023-11-21

申请号：US17735052

申请日：2022-05-02

Applicant: Socionext Inc.

Inventor： Hidetoshi Tanaka

IPC: H01L27/02 ,  H02H9/04

CPC classification number: H01L27/0248 ,  H02H9/046

Abstract: In an output circuit of a semiconductor integrated circuit device, an output transistor is placed apart from an ESD protection diode connected to an external output terminal, and a protection resistance is placed between them. The protection resistance is formed as a plurality of separate resistance regions, and taps supplying a power supply voltage to a substrate or a well are formed between the resistance regions. Noise applied to the external output terminal is attenuated by the protection resistance before reaching the output transistor and absorbed through the taps.

公开(公告)号：US11581302B2

公开(公告)日：2023-02-14

申请号：US16999933

申请日：2020-08-21

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi Tanaka

IPC: H01L27/02 ,  H01L29/06

Abstract: An ESD protection diode in a semiconductor device includes: a semiconductor substrate; a diode group that has a plurality of grouped VNW diodes, each of the VNW diodes having a VNW having a lower end and an upper end, that are formed on the semiconductor substrate and have a semiconductor material; and a top plate that is formed above the diode group and is a conductive layer electrically connected to the upper ends of the VNWs of the respective VNW diodes, and there is fabricated the semiconductor device that is capable of, even when large current flows through the VNW diode, suppressing current concentration and preventing damage of the VNW diode.

公开(公告)号：US10971581B2

公开(公告)日：2021-04-06

申请号：US16599907

申请日：2019-10-11

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi Tanaka

IPC: H01L29/06 ,  H01L27/02 ,  H01L29/786 ,  H01L29/78 ,  H01L27/088

Abstract: A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring formed on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring.

公开(公告)号：US10483348B2

公开(公告)日：2019-11-19

申请号：US15982775

申请日：2018-05-17

Applicant: SOCIONEXT, INC.

Inventor： Hidetoshi Tanaka

IPC: H01L31/113 ,  H01L31/119 ,  H01L29/06 ,  H01L27/02 ,  H01L29/786 ,  H01L29/78

Abstract: A semiconductor device has transistors formed on a substrate and including first and second impurity regions of a first conductivity type, a guard ring of a second conductivity type formed on the substrate and surrounding the transistors in a plan view, a wiring formed on and electrically connected to the guard ring, and a ground wiring faulted on the wiring and electrically connected to the wiring and the second impurity region. In a plan view, the transistor includes a first part having a distance that is a first distance from the guard ring, and a second part having a distance that is a second distance shorter than the first distance from the guard ring. In a plan view, the first part is located at a position separated from the ground wiring, and the second part is located at a position overlapping the ground wiring.