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公开(公告)号：US09240788B2
公开(公告)日：2016-01-19
申请号：US14550725
申请日：2014-11-21
Applicant: SOCIONEXT INC.
Inventor： Daisuke Suzuki , Masayuki Yamaguchi
IPC: H04B1/38 , H04L5/16 , H03K19/0175 , H03K19/173
CPC classification number: H03K19/017581 , H03K19/017509 , H03K19/1736
Abstract: A communication interface circuit includes a register and a register setting circuit. The register holds a data value for controlling characteristics of an electronic circuit element included in the communication interface circuit. The register setting circuit changes a wire connection state on the basis of a control signal. The register setting circuit inputs a variable data value to the register to detect the data value corresponding to the characteristics of the electronic circuit element in a first wire connection state, and sets the data value detected in the first wire connection state in the register on the basis of a fixed value in a second wire connection state. A control circuit outputs the above control signal.
Abstract translation: 通信接口电路包括寄存器和寄存器设置电路。 寄存器保持用于控制通信接口电路中包括的电子电路元件的特性的数据值。 寄存器设定电路根据控制信号改变接线状态。 寄存器设定电路向寄存器输入可变数据值，以检测与第一线连接状态下的电子电路元件的特性相对应的数据值，并将在第一线连接状态中检测到的数据值设置在寄存器中 在第二线连接状态下的固定值的基础。 控制电路输出上述控制信号。
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公开(公告)号：US10476710B2
公开(公告)日：2019-11-12
申请号：US16209616
申请日：2018-12-04
Applicant: SOCIONEXT INC.
Inventor： Masahiro Kudo , Daisuke Suzuki
Abstract: An equalizer circuit includes a first adder circuit adding an input signal and including an addition terminal and a subtraction terminal; a comparator circuit comparing an output signal of the first adder circuit; a latch circuit latching data output from the comparator circuit; a first digital/analog converter circuit which outputs a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value; a second digital/analog converter circuit which outputs a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and a switch circuit which switches a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.
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公开(公告)号：US10666234B2
公开(公告)日：2020-05-26
申请号：US16215210
申请日：2018-12-10
Applicant: SOCIONEXT INC.
Inventor： Daisuke Suzuki , Shigeaki Kawai
Abstract: A transmission circuit includes: a data generating circuit configured to generate data based on a clock signal; a clock generating circuit configured to supply the clock signal to the data generating circuit; and a duty ratio controlling circuit configured to detect a duty cycle distortion of the data output from the data generating circuit, and control a duty ratio of the clock signal based on a result of the detection.
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公开(公告)号：US20190109738A1
公开(公告)日：2019-04-11
申请号：US16209616
申请日：2018-12-04
Applicant: Socionext Inc.
Inventor： Masahiro KUDO , Daisuke Suzuki
Abstract: An equalizer circuit includes a first adder circuit adding an input signal and including an addition terminal and a subtraction terminal; a comparator circuit comparing an output signal of the first adder circuit; a latch circuit latching data output from the comparator circuit; a first digital/analog converter circuit which outputs a first signal corresponding to an absolute value of an equalizing coefficient, when the equalizing coefficient is a positive value; a second digital/analog converter circuit which outputs a second signal corresponding to an absolute value of the equalizing coefficient, when the equalizing coefficient is a negative value; and a switch circuit which switches a connection between a set of an output terminal of the first digital/analog converter circuit, an output terminal of the second digital/analog converter circuit, and a set of the addition terminal and the subtraction terminal, based on the data latched in the latch circuit.
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