公开(公告)号：US11699660B2

公开(公告)日：2023-07-11

申请号：US17180094

申请日：2021-02-19

Applicant: SOCIONEXT INC.

Inventor： Isaya Sobue ,  Hidetoshi Tanaka ,  Mai Tsukamoto

IPC: H01L23/528 ,  H01L27/02

CPC classification number: H01L23/5286 ,  H01L27/0292

Abstract: A semiconductor integrated circuit device includes a core region and an IO region on a chip. In an IO cell row placed in the IO region, a first power supply line extending in the X direction in a low power supply voltage region has a portion protruding to the core region. A signal IO cell has a reinforcing line that connects a second power supply line extending in the X direction in the low power supply voltage region and a third power supply line extending in the X direction in a high power supply voltage region, the reinforcing line extending in the Y direction in a layer above the second and third power supply lines.

公开(公告)号：US20220077137A1

公开(公告)日：2022-03-10

申请号：US17467069

申请日：2021-09-03

Applicant: SOCIONEXT INC.

Inventor： Hidetoshi TANAKA ,  Mai Tsukamoto

IPC: H01L27/02 ,  H01L23/522

Abstract: A semiconductor device includes a pad portion, a protection circuit, N wiring layers, and conductive vias connecting adjacent wiring layers, wherein, in a plan view, the semiconductor device includes a first area, a second area, and a third area, wherein the N wiring layers are provided to extend over the first area, the second area, and the third area, wherein a first wiring layer on a side of the pad portion is connected to the pad portion in the first area, and wherein an N-th wiring layer on a side of the protection circuit is connected to the protection circuit in the second area, and in the second area and the third area, where a total cross-sectional area of i-th conductive vias connecting an i-th wiring layer and an (i+1)-th wiring layer is denoted as Si, S1 is smaller than Sj for any j (j being 2 or more).