-
公开(公告)号：US20220038090A1
公开(公告)日：2022-02-03
申请号：US17370453
申请日：2021-07-08
Applicant: SOCIONEXT INC.
Inventor： David Hany Gaied MIKHAEL , Bernd Hans GERMANN , Ricardo DOLDAN LORENZO
Abstract: A leakage-current compensation circuit including: a first node for connection of a first component, a first leakage current flows through the first component and node with a given polarity, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node with a second leakage current flowing through the second component and node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first and second nodes to cause a compensation current, the magnitude of the compensation current dependent on the magnitude of the second leakage current; a differential amplifier connected in series with the second component along a current path carrying the second leakage current; and an AC coupling superimposing an AC-component of the first potential difference on the second potential difference.
-
公开(公告)号：US20250096779A1
公开(公告)日：2025-03-20
申请号：US18827261
申请日：2024-09-06
Applicant: Socionext Inc.
Inventor： David Hany Gaied MIKHAEL , Bernd Hans GERMANN , Ricardo DOLDAN LORENZO
Abstract: Polyphase filter circuitry including: an input node to receive an input signal VIN having a dominant frequency fPPF; and a common-source amplifier circuit. The common-source amplifier circuit includes a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor CPFF connected to its source terminal; and for the common-source amplifier circuit, the output resistance RM1 at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor CPFF are define the frequency response of the common-source amplifier circuit so that, based on the input signal VIN, a signal VLEAD is generated at the drain terminal of the transistor M1 which leads the input signal VIN in phase by a given phase shift ΔϕLEAD and a signal VLAG is generated at the source terminal of the transistor M1 which lags the input signal VIN in phase by a given phase shift ΔϕLAG.
-
公开(公告)号：US20220407525A1
公开(公告)日：2022-12-22
申请号：US17837516
申请日：2022-06-10
Applicant: Socionext Inc.
Inventor： David Hany Gaied MIKHAEL , Bernd Hans GERMANN , Ricardo DOLDAN LORENZO
Abstract: Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.
-
-
Search Results
3
records
(took 0.011 seconds)
