公开(公告)号：US20210193378A1

公开(公告)日：2021-06-24

申请号：US17088379

申请日：2020-11-03

Applicant: SOCIONEXT INC.

Inventor： David Hany Gaied MIKHAEL ,  Bernd Hans GERMANN

IPC: H01F27/34 ,  H01L49/02

Abstract: An inductor arrangement, comprising: a first pair of driven inductors configured to be driven to generate magnetic fields which are substantially in antiphase, and arranged relative to one another so that their magnetic fields substantially cancel one another at a first null line between those inductors; and a second pair of driven inductors configured to produce magnetic fields which are substantially in antiphase, and arranged relative to one another so that their magnetic fields substantially cancel one another at a second null line between those inductors, wherein the pairs of driven inductors are arranged relative to one another so that the first and second null lines intersect one another, with the first pair of driven inductors located substantially on the second null line and the second pair of inductors located substantially on the first null line.

公开(公告)号：US20220038090A1

公开(公告)日：2022-02-03

申请号：US17370453

申请日：2021-07-08

Applicant: SOCIONEXT INC.

Inventor： David Hany Gaied MIKHAEL ,  Bernd Hans GERMANN ,  Ricardo DOLDAN LORENZO

IPC: H03K17/16 ,  G05F1/46

Abstract: A leakage-current compensation circuit including: a first node for connection of a first component, a first leakage current flows through the first component and node with a given polarity, the magnitude of the first leakage current dependent on a first potential difference across the first component; a second component connected to a second node with a second leakage current flowing through the second component and node, the magnitude of the second leakage current dependent on a second potential difference across the second component; a current mirror connected to the first and second nodes to cause a compensation current, the magnitude of the compensation current dependent on the magnitude of the second leakage current; a differential amplifier connected in series with the second component along a current path carrying the second leakage current; and an AC coupling superimposing an AC-component of the first potential difference on the second potential difference.

公开(公告)号：US20210167782A1

公开(公告)日：2021-06-03

申请号：US17100350

申请日：2020-11-20

Applicant: SOCIONEXT INC.

Inventor： David Hany Gaied MIKHAEL ,  Bernd Hans GERMANN

IPC: H03L7/08 ,  H03L7/099 ,  H03C3/09 ,  H03B5/12

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

公开(公告)号：US20250096779A1

公开(公告)日：2025-03-20

申请号：US18827261

申请日：2024-09-06

Applicant: Socionext Inc.

Inventor： David Hany Gaied MIKHAEL ,  Bernd Hans GERMANN ,  Ricardo DOLDAN LORENZO

IPC: H03H17/02 ,  H03F3/193

Abstract: Polyphase filter circuitry including: an input node to receive an input signal VIN having a dominant frequency fPPF; and a common-source amplifier circuit. The common-source amplifier circuit includes a field-effect transistor M1 with its gate terminal connected to the input node and with a capacitor CPFF connected to its source terminal; and for the common-source amplifier circuit, the output resistance RM1 at the source terminal of the field-effect transistor M1 and the capacitance of the capacitor CPFF are define the frequency response of the common-source amplifier circuit so that, based on the input signal VIN, a signal VLEAD is generated at the drain terminal of the transistor M1 which leads the input signal VIN in phase by a given phase shift ΔϕLEAD and a signal VLAG is generated at the source terminal of the transistor M1 which lags the input signal VIN in phase by a given phase shift ΔϕLAG.

公开(公告)号：US20220407525A1

公开(公告)日：2022-12-22

申请号：US17837516

申请日：2022-06-10

Applicant: Socionext Inc.

Inventor： David Hany Gaied MIKHAEL ,  Bernd Hans GERMANN ,  Ricardo DOLDAN LORENZO

IPC: H03L7/099 ,  H03L7/089

Abstract: Phase Locked Loop, PLL, circuitry comprising a phase detector configured to generate a first pulse signal comprising at least one first pulse, a property of each first pulse being indicative of a phase difference between a reference signal and a feedback signal; a pulse repeater circuit configured, based on the first pulse signal, to generate a second pulse signal comprising, for each first pulse, a second pulse generated by repeating the corresponding first pulse; and an oscillator configured to generate the feedback signal and control a frequency of the feedback signal based on the second pulse signal.

公开(公告)号：US20220286089A1

公开(公告)日：2022-09-08

申请号：US17824537

申请日：2022-05-25

Applicant: SOCIONEXT INC.

Inventor： David Hany Gaied MIKHAEL ,  Bernd Hans GERMANN

IPC: H03B27/00 ,  H03L7/099

Abstract: Quadrature oscillator circuitry, comprising: a first differential oscillator circuit having differential output nodes and configured to generate a first pair of differential oscillator signals at those output nodes, respectively; a second differential oscillator circuit having differential output nodes and configured to generate a second pair of differential oscillator signals at those output nodes, respectively; and a cross-coupling circuit connected to cross-couple the first and second differential oscillator circuits. The cross-coupling circuit may comprise a pair of cross-coupled transistors.

公开(公告)号：US20190229676A1

公开(公告)日：2019-07-25

申请号：US16244010

申请日：2019-01-09

Applicant: SOCIONEXT INC.

Inventor： Bernd Hans GERMANN ,  Vamshi Krishna MANTHENA

IPC: H03B5/12 ,  H01L49/02 ,  H01L23/538 ,  H01L23/522 ,  H03L7/16

Abstract: In semiconductor integrated circuitry having metal layers and via layers sandwiched between adjacent said metal layers, a capacitor is formed from metal structures implemented in first to third metal layers. The metal structures comprise strips having widths parallel to the layers. The strips of the first layer form a first comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the strips being in a lower range of widths. The strips of the second layer form a second comb having a base strip and a plurality of finger strips extending from the base strip, the widths of the finger strips being in the lower range of widths. The width of each base strip formed in the second layer is in an intermediate range of widths; and the strips formed in the third layer have widths in a higher range of widths.