公开(公告)号：US20170264259A1

公开(公告)日：2017-09-14

申请号：US15456103

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  Saul DARZY

IPC: H03H7/38

CPC classification number: H03H7/38 ,  H03K19/0175 ,  H03M1/00

Abstract: There is disclosed herein integrated circuitry,comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analogue converter circuitry.

公开(公告)号：US20230034138A1

公开(公告)日：2023-02-02

申请号：US17859587

申请日：2022-07-07

Applicant: Socionext Inc.

Inventor： Saul DARZY ,  Pritty SKARIA

IPC: H03M1/10

Abstract: Alignment circuitry including a first clocked latch for receiving a synchronization signal having an enable edge and a target clock signal and outputting an enable signal having an enable edge corresponding to the enable edge of the synchronization signal and synchronized with the target clock signal; a second clocked latch for receiving the enable signal and a delayed target clock signal, being a version of the target clock signal having been delayed by a delay circuit of the clock-controlled circuitry, and outputting a re-timed enable signal having an enable edge corresponding to the enable edge of the enable signal and synchronized with the delayed target clock signal; and gating circuitry for receiving the delayed target clock signal and the re-timed enable signal and to start output of the delayed target clock signal at a timing defined by the enable edge of the re-timed enable signal for controlling the clock-controlled circuitry.

公开(公告)号：US20230036535A1

公开(公告)日：2023-02-02

申请号：US17850202

申请日：2022-06-27

Applicant: Socionext Inc.

Inventor： Saul DARZY ,  Ozcan TUNCTURK

IPC: H03K17/687 ,  H03M1/12 ,  H03M1/66

Abstract: A current-mode circuit, comprising: at least one switch unit, each switch unit comprising a field-effect transistor connected at its source terminal in series with an impedance and configured to carry a given current, wherein for each switch unit or for at least one of the switch units the impedance is a variable impedance; and an adjustment circuit configured, for each switch unit or for said at least one of the switch units, to adjust an impedance of the variable impedance to calibrate a predetermined property of the switch unit which is dependent on the field-effect transistor.

公开(公告)号：US20200007104A1

公开(公告)日：2020-01-02

申请号：US16410437

申请日：2019-05-13

Applicant: SOCIONEXT INC.

Inventor： Atheer Sami BARGHOUTHI ,  Saul DARZY

IPC: H03H7/00 ,  H02H9/04

Abstract: An interface circuit, comprising: a signal line having signal, auxiliary and connection nodes defined therealong, the connection node for connection to a transmission line; signal-handling circuitry connected to the signal line at the signal node; an auxiliary circuit connected to the signal line at the auxiliary node; a signal pair of inductors connected in series along the signal line adjacent to and either side signal node; and an auxiliary pair of inductors connected in series along the signal line adjacent to and either side of the auxiliary node, wherein: the signal pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kS; the pair of inductors are configured to have a mutual coupling defined by a coupling coefficient kA; and kS has a positive value and kA has a negative value.

公开(公告)号：US20230123260A1

公开(公告)日：2023-04-20

申请号：US17959887

申请日：2022-10-04

Applicant: Socionext Inc.

Inventor： Saul DARZY

IPC: H03M1/78 ,  H03M1/74

Abstract: Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.