公开(公告)号：US20170264304A1

公开(公告)日：2017-09-14

申请号：US15455901

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  Gavin Lambertus Allen ,  Bernd Hans Germann ,  Albert Hubert Dorner

IPC: H03L7/085

CPC classification number: H03L7/085 ,  G04F10/005 ,  H03L7/091

Abstract: There is disclosed herein current-mode circuitry for measuring a timing difference between first and second signals, the circuitry comprising: a tail node configured during a measurement operation to receive a current pulse in dependence upon the first signal; first and second nodes conductively connectable to said tail node along respective first and second paths; and steering circuitry configured during the measurement operation to control such connections between the tail node and the first and second nodes based on the second signal to steer the current pulse so that a first portion of the current pulse passes along the first path and a second portion of the current pulse passes along the second path in dependence upon the timing difference between said first and second signals; and a signal output unit configured to output a measurement-result signal indicating a measure of said timing difference based upon one or both of the first and second portions.

公开(公告)号：US20170264308A1

公开(公告)日：2017-09-14

申请号：US15455988

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： John James DANSON ,  Ian Juso DEDIC ,  Prabhu Ashwin Harold REBELLO

IPC: H03M1/10 ,  H03M1/38 ,  H03M1/12

CPC classification number: H03M1/0675 ,  H03M1/0678 ,  H03M1/1009 ,  H03M1/1076 ,  H03M1/1215 ,  H03M1/1225 ,  H03M1/1245 ,  H03M1/38

Abstract: There is disclosed herein analogue-to-digital converter circuitry, comprising a set of sub-ADC units each for carrying out analogue-to-digital conversion operations, the set comprising a given number of core sub-ADC units for carrying out said given number of core conversion operations. Also provided is control circuitry operable, when a said sub-ADC unit is determined to be a defective sub-ADC unit, to cause the core conversion operations to be carried by the sub-ADC units of the set sub-ADC units other than the defective sub-ADC unit.

公开(公告)号：US20160254800A1

公开(公告)日：2016-09-01

申请号：US15069878

申请日：2016-03-14

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  David Timothy Enright

IPC: H03H11/22 ,  H03K5/15 ,  H01L49/02

CPC classification number: H03H11/22 ,  G06F1/10 ,  H01F2017/0073 ,  H01L28/10 ,  H03K5/1506

Abstract: An integrated circuit comprising an inductor arrangement, the arrangement comprising: four inductors adjacently located in a group and arranged to define two rows and two columns, wherein: the integrated circuit is configured to cause two of those inductors diagonally opposite from one another in the arrangement to produce an electromagnetic field having a first phase, and to cause the other two of those inductors to produce an electromagnetic field having a second phase, the first and second phases being substantially in antiphase.

公开(公告)号：US20170264259A1

公开(公告)日：2017-09-14

申请号：US15456103

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  Saul DARZY

IPC: H03H7/38

CPC classification number: H03H7/38 ,  H03K19/0175 ,  H03M1/00

Abstract: There is disclosed herein integrated circuitry,comprising a signal path connected to a connection pad, for connection to external circuitry; and a termination circuit connected between the signal path and a voltage reference, wherein the termination circuit comprises a resistor and an inductor. The resistor and the inductor are connected together so as to compensate for parasitic capacitance associated with the connection pad. The signal path may carry an output signal from high-speed circuitry such as digital-to-analogue converter circuitry.

公开(公告)号：US20170264310A1

公开(公告)日：2017-09-14

申请号：US15455957

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  Prabhu Ashwin Harold REBELLO ,  John James DANSON

IPC: H03M1/38 ,  H03M1/00 ,  H03K3/013 ,  H02M3/07 ,  H03K5/24

CPC classification number: H03M1/38 ,  H02M3/07 ,  H03K3/013 ,  H03K5/2481 ,  H03K5/249 ,  H03M1/002

Abstract: There is disclosed herein charge-mode circuitry for use in a comparator to capture a difference between magnitudes of first and second input signals, the circuitry comprising: a tail node configured during a capture operation to receive a charge packet; first and second nodes conductively connectable to said tail node along respective first and second paths; and control circuitry configured during the capture operation to control such connections between the tail node and the first and second nodes based on the first and second input signals such that said charge packet is divided between said first and second paths in dependence upon the difference between magnitudes of the first and second input signals.

公开(公告)号：US20170264241A1

公开(公告)日：2017-09-14

申请号：US15455833

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  David Timothy ENRIGHT

IPC: H03B28/00 ,  H03M1/66 ,  H01L23/00 ,  H03M1/12

CPC classification number: H03B28/00 ,  H01L24/16 ,  H01L2224/16225 ,  H01L2924/14211 ,  H01L2924/14253 ,  H03B5/18 ,  H03B5/1805 ,  H03B5/1841 ,  H03B2200/0016 ,  H03K3/0315 ,  H03M1/12 ,  H03M1/66

Abstract: There is disclosed herein clock generation circuitry, in particular rotary travelling wave oscillator circuitry. Such circuitry comprises a pair of signal lines connected together to form a dosed loop and arranged such that they define at least one transition section where both said lines in a first portion of the pair cross from one lateral side of both said lines in a second portion of the pair to the other lateral side of both said lines in the second portion of the pair.

公开(公告)号：US20170264240A1

公开(公告)日：2017-09-14

申请号：US15456277

申请日：2017-03-10

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  Abdullah Mohd. Riazuddin Ahmed

IPC: H03B5/12 ,  H01L29/94 ,  H03B27/00

CPC classification number: H03B5/1256 ,  G06F1/10 ,  G06F3/05 ,  H01L29/94 ,  H03B5/1293 ,  H03B27/00 ,  H03K5/135

Abstract: There is disclosed herein integrated circuitry comprising a clock path for carrying a clock signal from a clock source to a circuit block, the circuit block being operable based on the clock signal. Clock buffer circuitry is provided along the clock path for buffering the clock signal. A tuneable inductance is connected to the clock path. A capacitor is connected to the clock path so as to form an AC coupling capacitor connected in series along the path, and is implemented between metal layers of the integrated circuitry.

公开(公告)号：US20160043052A1

公开(公告)日：2016-02-11

申请号：US14824967

申请日：2015-08-12

Applicant: SOCIONEXT INC.

Inventor： Ian Juso DEDIC ,  Ghazanfer ALI

IPC: H01L23/00 ,  H01L23/12

CPC classification number: H01L24/17 ,  H01L23/12 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/50 ,  H01L23/552 ,  H01L24/14 ,  H01L2224/16225 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A low-noise flip-chip package, comprising: a carrier substrate having first and second opposing main faces; and a flip-chip substrate connected in a face-down manner onto the first main face of the carrier substrate via a connection array, wherein: the flip-chip substrate comprises at least first and second circuitry portions spaced apart from one another; the flip-chip substrate comprises a substrate-contact boundary located between the first and second circuitry portions; and each of the first circuitry portion, the second circuitry portion and the substrate-contact boundary has its own separate signal-reference connection extending via a respective connection of the connection array through the carrier substrate to a respective electrical contact at the second main face of the carrier substrate for connection to a common signal-reference element in an external circuit.