公开(公告)号：US10784887B2

公开(公告)日：2020-09-22

申请号：US16719741

申请日：2019-12-18

Applicant: SOCIONEXT INC.

Inventor： Suhas Rattan

IPC: H03M1/78 ,  H03M1/38 ,  H03M1/06 ,  H03M1/80 ,  H03M1/12 ,  H03M1/00

Abstract: Controllable voltage-signal generation circuitry, including: a plurality of segment nodes connected together in series, each adjacent pair of segment nodes connected together via a corresponding coupling capacitor, an end one of the segment nodes serving as an output node; for each of the segment nodes, at least one segment capacitor having a first terminal connected to that segment node and a second terminal connected to a corresponding switch; and switch control circuitry, wherein: each switch is operable to connect the second terminal to one reference voltage source and then instead to another reference voltage source, to apply a voltage change at the second terminal; the reference voltage sources and switches configured such that for each segment node the same voltage change in magnitude is applied by each switch, and such that the voltage change is different in magnitude from the voltage change applied by each switch of another segment node.

公开(公告)号：US10917100B2

公开(公告)日：2021-02-09

申请号：US16719801

申请日：2019-12-18

Applicant: SOCIONEXT INC.

Inventor： Suhas Rattan

IPC: H03M1/10 ,  H03M1/06 ,  H03M1/00 ,  H03M1/38 ,  H02M3/07 ,  H03K3/013 ,  H03K5/24

Abstract: Comparator circuitry for use in a comparator to capture differences between magnitudes of a pair of comparator input signals in a series of capture operations defined by a reset signal, the circuitry comprising: latch circuitry, comprising a pair of latch input transistors which form corresponding parts of first and second current paths of the latch circuitry respectively, which current paths extend in parallel between high and low voltage sources, a pair of latch output nodes at corresponding positions along the first and second current paths of the latch circuitry respectively, and timing circuitry; and gain-stage circuitry, comprising a pair of cross-coupled gain-stage output transistors connected along respective first and second current paths of the gain-stage circuitry which extend in parallel between high and low voltage sources, and a pair of diode-connected gain-stage output transistors connected in parallel with the pair of cross-coupled gain-stage output transistors, respectively.