公开(公告)号：US20180041212A1

公开(公告)日：2018-02-08

申请号：US15725123

申请日：2017-10-04

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yasuhiro AGATA ,  Yoshinobu YAMAGAMI

IPC: H03K19/017 ,  H03K17/12 ,  H03K19/094 ,  H03K19/0952 ,  H01L21/00 ,  H01L29/00

CPC classification number: H03K19/01721 ,  H01L21/00 ,  H01L29/00 ,  H03K17/122 ,  H03K19/094 ,  H03K19/0952

Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

公开(公告)号：US20160211839A1

公开(公告)日：2016-07-21

申请号：US15080406

申请日：2016-03-24

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yasuhiro AGATA ,  Yoshinobu YAMAGAMI

IPC: H03K17/16 ,  H01L29/78

CPC classification number: H03K19/01721 ,  H01L21/00 ,  H01L29/00 ,  H03K17/122 ,  H03K19/094 ,  H03K19/0952

Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

Abstract translation: 本文公开了一种驱动器电路，其包括设置在第一和第二节点之间的第一组晶体管，并且包括其中n等于或大于1的晶体管的n个，以及与第一组并联设置的第二组晶体管 的晶体管，其中m为m以上且m为1以上且不等于n的晶体管，m个晶体管串联连接在一起。 第一组中的n沟道晶体管和第二组中的两个n沟道晶体管中的至少一个具有连接到输入节点的栅极。