公开(公告)号：US20160267963A1

公开(公告)日：2016-09-15

申请号：US15162321

申请日：2016-05-23

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C7/12

Abstract: A memory bank of a semiconductor memory device includes: a plurality of memory cells; first and second local bit lines; a differential amplifier configured to amplify a potential difference between the first and second local bit lines; a connector to which a global data line is connected; a first output circuit configured to selectively output, according to a potential level of the first local bit line, a first potential to the connector; and a second output circuit configured to selectively prevent, according to a potential level of the second local bit line, a potential of the connector from being affected by an output of the first output circuit and being equal to the first potential.

Abstract translation: 半导体存储器件的存储体包括：多个存储单元; 第一和第二局部位线; 差分放大器，被配置为放大第一和第二局部位线之间的电位差; 连接全球数据线的连接器; 第一输出电路，被配置为根据第一局部位线的电位有选择地向连接器输出第一电位; 以及第二输出电路，被配置为根据所述第二局部位线的电位水平选择性地防止所述连接器的电位受到所述第一输出电路的输出的影响并且等于所述第一电位。

公开(公告)号：US20180041212A1

公开(公告)日：2018-02-08

申请号：US15725123

申请日：2017-10-04

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yasuhiro AGATA ,  Yoshinobu YAMAGAMI

IPC: H03K19/017 ,  H03K17/12 ,  H03K19/094 ,  H03K19/0952 ,  H01L21/00 ,  H01L29/00

CPC classification number: H03K19/01721 ,  H01L21/00 ,  H01L29/00 ,  H03K17/122 ,  H03K19/094 ,  H03K19/0952

Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

公开(公告)号：US20150318042A1

公开(公告)日：2015-11-05

申请号：US14799509

申请日：2015-07-14

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE

IPC: G11C15/04 ,  G06F12/10

CPC classification number: G11C15/04 ,  G06F12/1027 ,  G06F2212/3042

Abstract: A comparison function-equipped memory element includes: a memory circuit that stores comparison object data; a comparison circuit that compares the comparison object data held in the memory circuit with comparison data and outputs the comparison result; and a write circuit that writes the comparison object data into the memory circuit under control of a write control signal during write operation, and overwrites the comparison data into the memory circuit when a mask control signal indicates mask operation during comparison operation.

Abstract translation: 具有比较功能的存储元件包括：存储比较对象数据的存储电路; 比较电路，将存储电路中保存的比较对象数据与比较数据进行比较，并输出比较结果; 以及在写入操作期间在写入控制信号的控制下将比较对象数据写入存储器电路的写入电路，并且当掩模控制信号在比较操作期间指示掩模操作时，将比较数据重写到存储器电路中。

公开(公告)号：US20160211839A1

公开(公告)日：2016-07-21

申请号：US15080406

申请日：2016-03-24

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yasuhiro AGATA ,  Yoshinobu YAMAGAMI

IPC: H03K17/16 ,  H01L29/78

CPC classification number: H03K19/01721 ,  H01L21/00 ,  H01L29/00 ,  H03K17/122 ,  H03K19/094 ,  H03K19/0952

Abstract: Disclosed herein is a driver circuit including a first group of transistors provided between first and second nodes and including n of the transistor(s) where n is equal to or greater than one, and a second group of transistors provided in parallel with the first group of transistors and including m of the transistor(s) where m is equal to or greater than one and not equal to n, the m transistors being connected together in series. The n-channel transistor in the first group and at least one of the two n-channel transistors in the second group have their gate connected to an input node.

Abstract translation: 本文公开了一种驱动器电路，其包括设置在第一和第二节点之间的第一组晶体管，并且包括其中n等于或大于1的晶体管的n个，以及与第一组并联设置的第二组晶体管 的晶体管，其中m为m以上且m为1以上且不等于n的晶体管，m个晶体管串联连接在一起。 第一组中的n沟道晶体管和第二组中的两个n沟道晶体管中的至少一个具有连接到输入节点的栅极。

公开(公告)号：US20160189756A1

公开(公告)日：2016-06-30

申请号：US15064381

申请日：2016-03-08

Applicant: SOCIONEXT INC.

Inventor： Tsuyoshi KOIKE ,  Yoshinobu YAMAGAMI

IPC: G11C7/06 ,  H01L27/105 ,  G11C5/14

CPC classification number: G11C7/062 ,  G11C5/148 ,  G11C7/065 ,  G11C7/12 ,  G11C11/419 ,  H01L27/105 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/785

Abstract: A cross-coupled circuit provided between first and second bit lines that form a bit line pair includes first to fourth fin transistors of p-channel type. The first transistor has its source connected to a first power supply and its gate connected to the second bit line. The second transistor has its source connected to the first power supply and its gate connected to the first bit line. The third transistor has its source connected to the first transistor's drain and its drain connected to the first bit line. The fourth transistor has its source connected to the second transistor's drain and its drain connected to the second bit line.

Abstract translation: 设置在形成位线对的第一和第二位线之间的交叉耦合电路包括p沟道型的第一至第四鳍式晶体管。 第一晶体管的源极连接到第一电源，其栅极连接到第二位线。 第二晶体管的源极连接到第一电源，其栅极连接到第一位线。 第三晶体管的源极连接到第一晶体管的漏极，其漏极连接到第一位线。 第四晶体管的源极连接到第二晶体管的漏极，其漏极连接到第二位线。