公开(公告)号：US20160148971A1

公开(公告)日：2016-05-26

申请号：US14899243

申请日：2014-06-16

Applicant: SOITEC

Inventor： Marcel BROEKAART ,  Laurent MARINIER

IPC: H01L27/146

CPC classification number: H01L27/14687 ,  H01L21/6835 ,  H01L21/78 ,  H01L25/50 ,  H01L27/14636 ,  H01L27/1464 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A process for transferring a buried circuit layer comprises taking a donor substrate comprising an internal etch stop zone and covered on its front side with a circuit layer, producing over the entire circumference of the donor substrate either a peripheral trench or a peripheral routing, this routing or trench being produced over a depth such that they pass entirely through the circuit layer and extend into the donor substrate, depositing on the circuit layer and on the routed side or on the walls of the trench a layer of an etch stop material that is selective with respect to etching of the circuit layer, without filling the trench, bonding a receiver substrate to the donor substrate, and thinning the donor substrate by etching its back side until reaching the etch stop zone so as to obtain the transfer of the buried circuit layer to the receiver substrate.

Abstract translation: 用于传送掩埋电路层的工艺包括取下包含内部蚀刻停止区的施主衬底，并在其前侧覆盖有电路层，在施主衬底的整个圆周上产生外围沟槽或外围路由，该布线 或沟槽在深度上产生，使得它们完全通过电路层并延伸到施主衬底中，在电路层上和在沟道侧或沟槽的壁上沉积有选择性的蚀刻停止材料层 关于电路层的蚀刻，而不填充沟槽，将接收器衬底接合到施主衬底，并且通过蚀刻其背面直到到达蚀刻停止区来稀释施主衬底，以获得掩埋电路层的传输 到接收器基板。

公开(公告)号：US20140065759A1

公开(公告)日：2014-03-06

申请号：US14067453

申请日：2013-10-30

Applicant: Soitec

Inventor： Marcel BROEKAART

IPC: H01L21/762 ,  H01L27/146

CPC classification number: H01L21/76251 ,  H01L21/2003 ,  H01L21/67092 ,  H01L23/544 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14 ,  H01L27/14601 ,  H01L27/14687 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2224/8313 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83

Abstract: A method for bonding first and second wafers by molecular adhesion. The method includes placing the wafers in an environment having a first pressure (P1) greater than a predetermined threshold pressure above which initiation of bonding wave propagation is prevented, bringing the first wafer and the second wafer into alignment and contact, and spontaneously initiating the propagation of a bonding wave between the wafers after they are in contact solely by reducing the pressure within the environment to a second pressure (P2) below the threshold pressure.

Abstract translation: 一种通过分子粘附将第一和第二晶片接合的方法。 该方法包括将晶片放置在具有大于预定阈值压力的第一压力（P1）的环境中，在该环境下，防止接合波传播的起始，使第一晶片和第二晶片对准和接触，并且自发地启动传播 只有通过将环境中的压力降低到低于阈值压力的第二压力（P2），晶片之间的结合波在它们接触之后。

公开(公告)号：US20130105932A1

公开(公告)日：2013-05-02

申请号：US13718624

申请日：2012-12-18

Applicant: Soitec

Inventor： Marcel BROEKAART

IPC: H01L27/14

CPC classification number: H01L21/76251 ,  H01L21/2003 ,  H01L21/67092 ,  H01L23/544 ,  H01L24/83 ,  H01L24/94 ,  H01L25/50 ,  H01L27/14 ,  H01L27/14601 ,  H01L27/14687 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2223/54493 ,  H01L2224/8313 ,  H01L2224/83894 ,  H01L2224/94 ,  H01L2924/3512 ,  H01L2924/00 ,  H01L2224/83

Abstract: A three-dimensional composite structure that includes a wafer and layer of semiconductor crystalline material bonded thereto, with the layer including first and second series of microcomponents on the first and second faces respectively, with the microcomponents being in alignment such that any residual alignment offsets between the first and second series of microcomponents are less than 100 nm homogeneously over the entire surface of the structure.

Abstract translation: 一种三维复合结构，其包括晶片和结合到其上的半导体结晶材料层，所述层分别包括第一和第二表面上的第一和第二系列微组件，微组件对准，使得任何残留对准偏移 第一和第二系列微组件在结构的整个表面上均匀地小于100nm。