公开(公告)号：US12056428B1

公开(公告)日：2024-08-06

申请号：US18571739

申请日：2023-01-03

Applicant: SOUTHEAST UNIVERSITY

Inventor： Peng Cao ,  Guoqing He ,  Tai Yang

IPC: G06F30/3315 ,  G06F119/12

CPC classification number: G06F30/3315 ,  G06F2119/12

Abstract: A post-routing path delay prediction method for a digital integrated circuit is provided. First, physical design and static timing analysis are performed on a circuit by a commercial physical design tool and a static timing analysis tool, timing and physical information of a path is extracted before routing of the circuit to be used as input features of a prediction model, then the timing and physical correlation of all stages of cells in the path is captured by a transformer network, a predicted post-routing path delay is calibrated by a residual prediction structure, and finally, a final predicted post-routing path delay is output.