SERIAL DATA INTERFACE WITH REDUCED LOOP DELAY

    公开(公告)号:US20210248104A1

    公开(公告)日:2021-08-12

    申请号:US17143679

    申请日:2021-01-07

    Abstract: A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.

Patent Agency Ranking