公开(公告)号：US08994416B2

公开(公告)日：2015-03-31

申请号：US14045642

申请日：2013-10-03

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: H03B19/00 ,  H03K3/02 ,  H03K3/037

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US09160336B2

公开(公告)日：2015-10-13

申请号：US13715721

申请日：2012-12-14

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Jain ,  Chittoor Parthasarathy ,  Kallol Chatterjee

IPC: G06F17/50 ,  H03K19/003

CPC classification number: H03K19/003 ,  G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

Abstract translation: 公开了一种用于在电路中提供关键路径复制系统的系统和方法。 通过确定电路中的关键路径，产生关键路径复制电路，生成电路蓝图以及创建蓝图电路来创建关键路径复制系统。 该电路包括具有功能逻辑元件的功能逻辑模块和具有逻辑元件的复制逻辑模块。 每个逻辑元件被配置为复制一个或多个功能逻辑元件并处理测试信号。 复制错误检测模块分析处理的信号以确定是否发生定时冲突。 在一些实施例中，副本逻辑模块还包括一个或多个加载模块。 复制控制器可以基于报告的错误来修改电路的操作。 复制模式选择模块将副本逻辑模块设置为老化测试模式或定时传感器模式。

公开(公告)号：US20150169394A1

公开(公告)日：2015-06-18

申请号：US14631128

申请日：2015-02-25

Applicant: STMicroelectronics International N.V.

Inventor： Chittoor Parthasarathy ,  Abhishek Jain

IPC: G06F11/07

CPC classification number: G06F11/0751 ,  G06F11/1608 ,  H03K3/0375

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

Abstract translation: 电路的实施例包括数据锁存器和多个级联锁存器，其中多个级联锁存器中的第一个锁存器被配置为从数据锁存器接收第一信号，并且每个后续级联锁存器被配置为接收数据锁存器的数据输出信号 一个先前的级联锁存器和一个错误检测电路，配置成接收相应的数据输出信号，并在此基础上检测级联锁存器工作中的错误。

公开(公告)号：US09798599B2

公开(公告)日：2017-10-24

申请号：US14631128

申请日：2015-02-25

Applicant: STMicroelectronics International N.V.

Inventor： Chittoor Parthasarathy ,  Abhishek Jain

IPC: G06F11/00 ,  G06F11/14 ,  G06F11/30 ,  G06F11/07 ,  H03K3/037 ,  G06F11/16

CPC classification number: G06F11/0751 ,  G06F11/1608 ,  H03K3/0375

Abstract: An embodiment of a circuit includes a data latch and a plurality of cascaded latches, wherein a first of the plurality of cascaded latches is configured to receive a first signal from the data latch and each subsequent cascaded latch is configured to receive a data output signal of a preceding cascaded latch, and an error-detection circuit configured to receive the respective data output signals and detect error in operation of the cascaded latches based thereon.

公开(公告)号：US20160147545A1

公开(公告)日：2016-05-26

申请号：US14549332

申请日：2014-11-20

Applicant: STMicroelectronics International N.V.

Inventor： Abhishek Jain ,  Chittoor Parthasarathy

IPC: G06F9/445 ,  G06F11/34 ,  G06F11/30

CPC classification number: G06F9/44505 ,  G06F11/008 ,  G06F11/3024 ,  G06F11/3051 ,  G06F11/3055 ,  G06F11/3433

Abstract: An embodiment is a device including a processor having a plurality of cores, each of the plurality of cores including a real-time monitoring circuit, each of the real-time monitoring circuits configured to determine a status of the respective core and generate status signals based on the determined status in the respective core. The device further comprising a controller configured to: receive the status signals from real-time monitoring circuits of the plurality of cores; and configure an operation of each of the plurality of cores based on their respective status signals.

Abstract translation: 实施例是包括具有多个核的处理器的装置，所述多个核心中的每一个包括实时监视电路，所述实时监视电路中的每一个被配置为确定各个核心的状态并基于 在各自核心的确定状态。 该装置还包括控制器，其被配置为：从多个核心的实时监控电路接收状态信号; 并且基于它们各自的状态信号来配置多个核心中的每一个的操作。

公开(公告)号：US20140167812A1

公开(公告)日：2014-06-19

申请号：US13715721

申请日：2012-12-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Abhishek Jain ,  Chittoor Parthasarathy ,  Kallol Chatterjee

IPC: H03K19/003 ,  G06F17/50

CPC classification number: H03K19/003 ,  G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

Abstract translation: 公开了一种用于在电路中提供关键路径复制系统的系统和方法。 通过确定电路中的关键路径，产生关键路径复制电路，生成电路蓝图以及创建蓝图电路来创建关键路径复制系统。 该电路包括具有功能逻辑元件的功能逻辑模块和具有逻辑元件的复制逻辑模块。 每个逻辑元件被配置为复制一个或多个功能逻辑元件并处理测试信号。 复制错误检测模块分析处理的信号以确定是否发生定时冲突。 在一些实施例中，副本逻辑模块还包括一个或多个加载模块。 复制控制器可以基于报告的错误来修改电路的操作。 复制模式选择模块将副本逻辑模块设置为老化测试模式或定时传感器模式。