公开(公告)号：US08994416B2

公开(公告)日：2015-03-31

申请号：US14045642

申请日：2013-10-03

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics SA

Inventor： Chittoor Parthasarathy ,  Nitin Chawla ,  Kallol Chatterjee ,  Pascal Urard

IPC: H03B19/00 ,  H03K3/02 ,  H03K3/037

CPC classification number: H03K3/02 ,  H03K3/0375

Abstract: Adaptive scaling digital techniques attempt to place the system close to the timing failure so as to maximize energy efficiency. Rapid recovery from potential failures is usually by slowing the system clock and/or providing razor solutions (instruction replay.) These techniques compromise the throughput. This application presents a technique to provide local in-situ fault resilience based on dynamic slack borrowing. This technique is non-intrusive (needs no architecture modification) and has minimal impact on throughput.

Abstract translation: 自适应缩放数字技术试图使系统接近定时故障，以最大限度地提高能量效率。 潜在故障的快速恢复通常是通过减慢系统时钟和/或提供剃须刀解决方案（指令重放）。这些技术会损害吞吐量。 该应用提出了一种基于动态松弛借贷提供本地原位故障恢复能力的技术。 这种技术是非侵入式的（不需要架构修改），对吞吐量影响最小。

公开(公告)号：US11323131B2

公开(公告)日：2022-05-03

申请号：US17089090

申请日：2020-11-04

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha ,  Kallol Chatterjee

IPC: H03M3/00 ,  H03K7/08

Abstract: A delay chain circuit with series coupled delay elements receives a reference clock signal and outputs phase-shifted clock signals. A multiplexer circuit receives the phase-shifted clock signals and selects among the phase-shifted clock signals for output as in response to a selection signal. The selection signal is generated by a control circuit from a periodic signal having a triangular wave profile. A sigma-delta modulator converts the periodic signal to a digital signal, and an integrator circuit integrates the digital signal to output the selection signal. The selected phase-shifted clock signal is applied as the reference signal to a phase locked loop which generates a spread spectrum clock signal.

公开(公告)号：US20160181978A1

公开(公告)日：2016-06-23

申请号：US14576535

申请日：2014-12-19

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Gauri Mittal ,  Kallol Chatterjee ,  Pallavi Muktesh ,  Nitin Jain ,  Pradeep Kumar Badrathwal

IPC: H03B5/36

CPC classification number: H03B5/364 ,  H03B5/366 ,  H03B2200/0012 ,  H03B2200/0038

Abstract: A circuit includes an oscillator circuit to receive a bias current and generate an oscillating signal at an output node. A current differencing circuit subtracts a current at the output node from a reference current to generate a first current. In addition, a current mirroring circuit mirrors the first current to generate the bias current. An inverter stage is coupled to the output node, and includes an input branch configured to receive the oscillating signal and generate first and second control signals based upon the oscillating signal. At least one amplifying branch receives the first and second control signals and amplifies the first and second control signals. An output branch receives the amplified first and second control signals and generates an amplified version of the oscillating signal based upon the amplified first and second control signals.

Abstract translation: 电路包括用于接收偏置电流并在输出节点产生振荡信号的振荡器电路。 电流差分电路从参考电流中减去输出节点处的电流以产生第一电流。 此外，电流镜像电路反射第一电流以产生偏置电流。 逆变器级耦合到输出节点，并且包括被配置为接收振荡信号并基于振荡信号产生第一和第二控制信号的输入分支。 至少一个放大支路接收第一和第二控制信号并放大第一和第二控制信号。 输出分支接收放大的第一和第二控制信号，并且基于放大的第一和第二控制信号产生振荡信号的放大版本。

公开(公告)号：US08981817B2

公开(公告)日：2015-03-17

申请号：US13926748

申请日：2013-06-25

Applicant: STMicroelectronics International N.V. ,  STMicroelectronics (Crolles 2) SAS

Inventor： Vinod Kumar ,  Pradeep Kumar Badrathwal ,  Saiyid Mohammad Irshad Rizvi ,  Paras Garg ,  Kallol Chatterjee ,  Pierre Dautriche

IPC: H03K3/00

CPC classification number: H03K19/00384

Abstract: A circuit having a centralized PT compensation circuit to provide compensation signals to localized I/O blocks on the chip. Process variations and temperature variations tend to be approximately uniform across an integrated circuit chip. Thus, a single, centralized PT compensation circuit may be used instead of one PT compensation circuit per I/O section as with solutions of the past. Further, the PT compensation circuit may generate a digital code indicative of the effects of process and temperature. Further yet, each section of I/O block may have a local voltage compensation circuit to compensate the voltage variation of the I/O block. The voltage compensation circuit utilizes an independent reference voltage. The reference voltage is generated by the PT compensation circuit, which is placed centrally in the IC chip and hence any need to repeat the reference generation for each I/O block is eliminated.

Abstract translation: 具有集中PT补偿电路以向芯片上的局部I / O块提供补偿信号的电路。 整个集成电路芯片的工艺变化和温度变化趋向于大致均匀。 因此，与过去的解决方案一样，可以使用单个集中式PT补偿电路来代替每个I / O部分的一个PT补偿电路。 此外，PT补偿电路可以产生指示过程和温度的影响的数字代码。 此外，I / O块的每个部分可以具有用于补偿I / O块的电压变化的局部电压补偿电路。 电压补偿电路采用独立的参考电压。 参考电压由放置在IC芯片中央的PT补偿电路产生，因此不需要重复每个I / O块的参考生成。

公开(公告)号：US12136917B2

公开(公告)日：2024-11-05

申请号：US18151337

申请日：2023-01-06

Applicant: STMicroelectronics International N.V.

Inventor： Kallol Chatterjee ,  Rohit Kumar Gupta

IPC: H03K19/0185

Abstract: Provided is a voltage level shifter that operates in sub-threshold voltages. The level shifter includes a level shifting stage. The level shifting stage receives a first signal from a first voltage domain and outputs a second signal to a second voltage domain. The level shifter includes a first auxiliary stage. In response to the first signal having a first voltage level corresponding to a first logical state and a first node of the level shifting stage having a supply voltage level, the first auxiliary stage sources current to a second node of the level shifting stage. Sourcing the current to the second node accelerates a transition of the first node to a reference voltage. The level shifting stage outputs a second signal to a second voltage domain.

公开(公告)号：US20180287620A1

公开(公告)日：2018-10-04

申请号：US15471483

申请日：2017-03-28

Applicant: STMicroelectronics International N.V.

Inventor： Gagan Midha ,  Kallol Chatterjee

IPC: H03L7/093 ,  H03M3/00 ,  H03L7/081 ,  H03L7/08

Abstract: A phase locked loop (PLL) circuit disclosed herein includes a phase detector receiving a reference frequency signal and a feedback frequency signal, and configured to output a digital signal indicative of a phase difference between the reference frequency signal and the feedback frequency signal. A digital loop filter filters the digital signal. A digital to analog converter converts the filtered digital signal to a control signal. An oscillator generates a PLL clock signal based on the control signal. A sigma-delta modulator modulates a divider signal as a function of a frequency control word. A divider divides the PLL clock signal based on the divider signal, and generates a noisy feedback frequency signal based thereupon. A noise filtering block removes quantization noise from the noisy feedback frequency signal to thereby generate the feedback frequency signal.

公开(公告)号：US09054637B1

公开(公告)日：2015-06-09

申请号：US14152523

申请日：2014-01-10

Applicant: STMicroelectronics International N.V.

Inventor： Gauri Mittal ,  Kallol Chatterjee

IPC: H03B5/36 ,  H03B5/04 ,  H03B5/06

CPC classification number: H03B5/364 ,  H03B5/04 ,  H03B5/06 ,  H03B2200/0012 ,  H03B2200/0038 ,  H03B2200/0066 ,  H03B2200/0094

Abstract: An amplitude limiting circuit for a crystal oscillator circuit includes a current source configured to supply drive current to the crystal oscillator circuit and a current sensing circuit configured to sense operating current in an inverting transistor of the crystal oscillator circuit. The current comparison circuit functions to compare the sensed operating current to at least a reference current and generate an output signal. A current control circuit generates a control signal for controlling operation of the current source in response to the output signal.

Abstract translation: 晶体振荡器电路的振幅限制电路包括被配置为向晶体振荡器电路提供驱动电流的电流源和被配置为感测晶体振荡器电路的反相晶体管中的工作电流的电流感测电路。 当前比较电路用于将感测的工作电流与至少参考电流进行比较，并产生输出信号。 电流控制电路响应于输出信号产生用于控制电流源的操作的控制信号。

公开(公告)号：US12209919B1

公开(公告)日：2025-01-28

申请号：US18406551

申请日：2024-01-08

Applicant: STMicroelectronics International N.V.

Inventor： Pijush Kanti Panja ,  Kallol Chatterjee ,  Atul Dwivedi

IPC: H02K17/14 ,  G01K7/01 ,  H03K17/14 ,  H03K19/003 ,  H03M1/12

Abstract: A method for determining temperature of a chip, includes generating a first voltage and a second voltage using a pair of bipolar-junction transistors, and generating a third voltage using another bipolar-junction transistor. When a most recent bit of a bitstream is a logic-zero, the difference between the first and second voltages is sampled using a switched-capacitor input-sampling circuit, and a difference between the first and second voltages is integrated, to produce a proportional-to-absolute-temperature voltage. The proportional-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. When the most recent bit of the bitstream is a logic-one, the third voltage is sampled using the switched-capacitor input-sampling circuit, and the third voltage is integrated, to produce a complementary-to-absolute-temperature voltage. The complementary-to-absolute-temperature voltage is quantized to produce a next bit of the bitstream. The bitstream is filtered and decimated to produce an output code representative of the temperature of the chip.

公开(公告)号：US10530366B1

公开(公告)日：2020-01-07

申请号：US16503960

申请日：2019-07-05

Applicant: STMicroelectronics International N.V.

Inventor： Atul Dwivedi ,  Paras Garg ,  Kallol Chatterjee

IPC: H03K19/007 ,  H03K19/0185 ,  G01R31/317

Abstract: A low-voltage-differential-signaling (LVDS) fault detector includes first and second LVDS lines, and a window comparator provides a first output indicating whether a difference between voltages at the first and second LVDS lines is greater than a threshold voltage, and a second output indicating whether a difference between the voltages at the second and first LVDS lines is greater than the threshold voltage. A charge circuit charges a capacitive node when either the first or second output is at a logic low, and discharges the capacitive node when neither the first nor second output is at a logic low. A Schmitt trigger generates a fault flag if charge on the capacitive node falls to a threshold.

公开(公告)号：US20140167812A1

公开(公告)日：2014-06-19

申请号：US13715721

申请日：2012-12-14

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Abhishek Jain ,  Chittoor Parthasarathy ,  Kallol Chatterjee

IPC: H03K19/003 ,  G06F17/50

CPC classification number: H03K19/003 ,  G06F17/5045 ,  G06F2217/12 ,  Y02P90/265

Abstract: Disclosed is a system and method for providing a critical path replica system in a circuit. A critical path replica system is created by determining a critical path in a circuit, generating a critical path replica circuit, generating a circuit blueprint, and creating the blueprinted circuit. The circuit comprises a functional logic module having functional logic elements and replica logic modules having logic elements. Each logic element is configured to replicate one or more of the functional logic elements and process a test signal. A replica error detection module analyzes the processed signal to determine whether a timing violation has occurred. In some embodiments, the replica logic module further comprises one or more load modules. A replica controller may modify operation of the circuit based on reported errors. A replica mode select module sets the replica logic module to an aging test mode or a timing sensor mode.

Abstract translation: 公开了一种用于在电路中提供关键路径复制系统的系统和方法。 通过确定电路中的关键路径，产生关键路径复制电路，生成电路蓝图以及创建蓝图电路来创建关键路径复制系统。 该电路包括具有功能逻辑元件的功能逻辑模块和具有逻辑元件的复制逻辑模块。 每个逻辑元件被配置为复制一个或多个功能逻辑元件并处理测试信号。 复制错误检测模块分析处理的信号以确定是否发生定时冲突。 在一些实施例中，副本逻辑模块还包括一个或多个加载模块。 复制控制器可以基于报告的错误来修改电路的操作。 复制模式选择模块将副本逻辑模块设置为老化测试模式或定时传感器模式。