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    SEMICONDUCTOR POWER DEVICE WITH CORRESPONDING PACKAGE AND RELATED MANUFACTURING PROCESS
    3.
    发明申请
    SEMICONDUCTOR POWER DEVICE WITH CORRESPONDING PACKAGE AND RELATED MANUFACTURING PROCESS 审中-公开

    公开(公告)号：US20190311976A1

    公开(公告)日：2019-10-10

    申请号：US16370193

    申请日：2019-03-29

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Francesco SALAMONE ,  Cristiano Gianluca STELLA

    IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

    Abstract: A semiconductor power device has: a die, with a front surface and a rear surface, and with an arrangement of projecting regions on the front surface, which define between them windows arranged within which are contact regions; and a package, which houses the die inside it. A metal frame has a top surface and a bottom surface; the die is carried by the frame on the top surface; an encapsulation coating coats the frame and the die. A first insulation multilayer is arranged above the die and is formed by an upper metal layer, a lower metal layer, and an intermediate insulating layer; the lower metal layer is shaped according to an arrangement of the projecting regions and has contact projections, which extend so as to electrically contact the contact regions, and insulation regions, interposed between the contact projections, in positions corresponding to the projecting regions.

    PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF
    4.
    发明公开
    PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF 审中-公开

    公开(公告)号：US20240136260A1

    公开(公告)日：2024-04-25

    申请号：US18493686

    申请日：2023-10-23

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Cristiano Gianluca STELLA ,  Fabio RUSSO

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

    CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49527 ,  H01L23/49562 ,  H01L23/49575

    Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

    POWER SEMICONDUCTOR DEVICE WITH A DOUBLE ISLAND SURFACE MOUNT PACKAGE
    5.
    发明申请
    POWER SEMICONDUCTOR DEVICE WITH A DOUBLE ISLAND SURFACE MOUNT PACKAGE 有权

    公开(公告)号：US20210159161A1

    公开(公告)日：2021-05-27

    申请号：US17142738

    申请日：2021-01-06

    Applicant: STMicroelectronics S.r.l.

    Inventor： Cristiano Gianluca STELLA ,  Agatino MINOTTI

    IPC: H01L23/498 ,  H01L23/373

    Abstract: A power semiconductor device including a first and second die, each including a plurality of conductive contact regions and a passivation region including a number of projecting dielectric regions and a number of windows. Adjacent windows are separated by a corresponding projecting dielectric region with each conductive contact region arranged within a corresponding window. A package of the surface mount type houses the first and second dice. The package includes a first bottom insulation multilayer and a second bottom insulation multilayer carrying, respectively, the first and second dice. A covering metal layer is arranged on top of the first and second dice and includes projecting metal regions extending into the windows to couple electrically with corresponding conductive contact regions. The covering metal layer moreover forms a number of cavities, which are interposed between the projecting metal regions so as to overlie corresponding projecting dielectric regions.

    POWER MOSFET DEVICE AND MANUFACTURING PROCESS THEREOF
    6.
    发明申请
    POWER MOSFET DEVICE AND MANUFACTURING PROCESS THEREOF 审中-公开

    公开(公告)号：US20190109225A1

    公开(公告)日：2019-04-11

    申请号：US16154411

    申请日：2018-10-08

    Applicant: STMICROELECTRONICS S.R.L.

    Inventor： Fabio RUSSO ,  Cristiano Gianluca STELLA

    IPC: H01L29/78 ,  H01L29/10 ,  H01L29/08 ,  H01L23/00 ,  H01L23/495 ,  H01L23/538

    Abstract: A MOSFET device is integrated in a body of semiconductor material of a first conductivity type accommodating a body region, of a second conductivity type, and a source region, of the first conductivity type. A gate region extends over the top surface of the body; a source pad extends over the first top surface and is electrically coupled to the source region, a first gate pad extends over the first main surface, alongside the source pad, and is electrically coupled to the gate region; a drain pad extends over the rear surface and is electrically coupled to the body; a second gate pad extends over the rear surface, alongside the drain pad; and a conductive via extends through the body and electrically couples the gate region to the second gate pad.

    PACKAGED POWER ELECTRONIC DEVICE, IN PARTICULAR BRIDGE CIRCUIT COMPRISING POWER TRANSISTORS, AND ASSEMBLING PROCESS THEREOF
    9.
    发明申请
    PACKAGED POWER ELECTRONIC DEVICE, IN PARTICULAR BRIDGE CIRCUIT COMPRISING POWER TRANSISTORS, AND ASSEMBLING PROCESS THEREOF 有权

    公开(公告)号：US20210037674A1

    公开(公告)日：2021-02-04

    申请号：US16934991

    申请日：2020-07-21

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Cristiano Gianluca STELLA ,  Francesco SALAMONE

    IPC: H05K7/20 ,  H01L23/373 ,  H01L25/07

    Abstract: The device has a first support element forming a first thermal dissipation surface and carrying a first power component; a second support element forming a second thermal dissipation surface and carrying a second power component, a first contacting element superimposed to the first power component; a second contacting element superimposed to the second power component; a plurality of leads electrically coupled with the power components through the first and/or the second support elements; and a thermally conductive body arranged between the first and the second contacting elements. The first and the second support elements and the first and the second contacting elements are formed by electrically insulating and thermally conductive multilayers.

    PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF
    10.
    发明公开
    PACKAGED HIGH VOLTAGE MOSFET DEVICE WITH CONNECTION CLIP AND MANUFACTURING PROCESS THEREOF 审中-公开

    公开(公告)号：US20240234263A9

    公开(公告)日：2024-07-11

    申请号：US18493686

    申请日：2023-10-24

    Applicant: STMICROELECTRONICS S.r.l.

    Inventor： Cristiano Gianluca STELLA ,  Fabio RUSSO

    IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

    CPC classification number: H01L23/49568 ,  H01L21/4825 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/49527 ,  H01L23/49562 ,  H01L23/49575

    Abstract: An HV MOSFET device has a body integrating source conductive regions. Projecting gate structures are disposed above the body, laterally offset with respect to the source conductive regions. Source contact regions, of a first metal, are arranged on the body in electric contact with the source conductive regions, and source connection regions, of a second metal, are arranged above the source contact regions and have a height protruding with respect to the projecting gate structures. A package includes a metal support bonded to a second surface of the body, and a dissipating region, above the first surface of the semiconductor die. The dissipating region includes a conductive plate having a planar face bonded to the source connection regions and spaced from the projecting gate structures. A package mass of dielectric material is disposed between the support and the dissipating region and incorporates the semiconductor die. The dissipating region is a DBC-type insulation multilayer.

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