公开(公告)号：US20220059369A1

公开(公告)日：2022-02-24

申请号：US17407612

申请日：2021-08-20

Applicant: STMicroelectronics S.r.l.

Inventor： Marco ROVITTO ,  Pierangelo MAGNI ,  Fabio MARCHISI

IPC: H01L21/56 ,  H01L21/67 ,  H01L21/48

Abstract: A semiconductor die is attached to a die pad of a leadframe. The semiconductor die attached to the die pad is arranged in a molding cavity between complementary first and second mold portions. Package material is injected into the molding cavity via at least one injection channel provided in one of the complementary first and second mold portions. Air is evacuated from the molding cavity via at least one air venting channel provided in the other of the complementary first and second mold portions. An exit from the at least one air venting channel may be blocked by a retractable stopper during the injection of the package material.

公开(公告)号：US20220059368A1

公开(公告)日：2022-02-24

申请号：US17398710

申请日：2021-08-10

Applicant: STMicroelectronics S.r.l.

Inventor： Fulvio Vittorio FONTANA ,  Marco ROVITTO

IPC: H01L21/48 ,  H01L21/67 ,  H01L23/495

Abstract: At least one semiconductor chip or die is held within at a chip retaining formation provided in a chip holding device. The chip holding device is then positioned with the at least one semiconductor chip or die arranged facing a chip attachment location in a chip mounting substrate. This positioning produces a cavity between the at least one semiconductor chip or die arranged at the chip retaining formation and the chip attachment location in the chip mounting substrate. A chip attachment material is dispensed into the cavity. Once cured, the chip attachment material attaches the at least one semiconductor chip or die onto the substrate at the chip attachment location in the chip mounting substrate.

公开(公告)号：US20240178007A1

公开(公告)日：2024-05-30

申请号：US18516745

申请日：2023-11-21

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Marco ROVITTO

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/31 ,  H01L23/495

CPC classification number: H01L21/566 ,  H01L21/4825 ,  H01L23/3107 ,  H01L23/49503 ,  H01L23/4952

Abstract: One or more semiconductor dice are arranged on a die pad of a leadframe having an array of electrically conductive leads around the die pad. A pattern of electrically conductive wires is provided to couple the semiconductor die or dice with electrically conductive leads in the array around the die pad. An encapsulation of insulating material is provided to encapsulate the semiconductor die or dice arranged on the die pad and the pattern of electrically conductive wires. Providing the encapsulation comprises: a first encapsulation step wherein a first mass of encapsulation material is transferred onto the semiconductor die or dice arranged on the die pad and onto the pattern of electrically conductive wires to form a core portion of the encapsulation that fully encapsulates the die or dice and the electrically conductive wires, that are thus retained in position by the first mass of encapsulation material, and a second encapsulation step wherein a second mass of encapsulation material is molded onto the core portion of the encapsulation to provide a shell portion of the encapsulation around the core portion of the encapsulation.

公开(公告)号：US20230360928A1

公开(公告)日：2023-11-09

申请号：US18140290

申请日：2023-04-27

Applicant: STMicroelectronics S.r.l.

Inventor： Marco ROVITTO ,  Dario VITELLO

IPC: H01L21/56 ,  H01L21/48 ,  H01L23/00 ,  H01L23/495 ,  H01L23/498 ,  H01L21/768

CPC classification number: H01L21/565 ,  H01L21/4825 ,  H01L23/562 ,  H01L23/49513 ,  H01L23/49548 ,  H01L23/49827 ,  H01L21/76894 ,  H01L21/4842

Abstract: A semiconductor die is attached on a die mounting surface of a substrate. An insulating encapsulation of laser direct structuring (LDS) material is molded onto the substrate and the semiconductor die. The insulating encapsulation of LDS material has a front surface including a first portion and a second portion separated by gaps therebetween. Laser direct structuring processing is applied to the first portion of the front surface to structure in the encapsulation of LDS material electrically conductive formations including electrically conductive lines over the front surface and to the second portion of the front surface of the encapsulation of LDS material to form thereon a reinforcing warp-countering structure. The separation gaps are left exempt from laser direct structuring processing and the reinforcing warp-countering structure is electrically insulated from the electrically conductive lines by LDS material left exempt from laser direct structuring processing at the separation gaps.

公开(公告)号：US20220392863A1

公开(公告)日：2022-12-08

申请号：US17833233

申请日：2022-06-06

Applicant: STMicroelectronics S.r.l.

Inventor： Antonio BELLIZZI ,  Marco ROVITTO

IPC: H01L23/00 ,  H01L23/367 ,  H01L23/31 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor chip is arranged on a region of laser direct structuring (LDS) material of a laminar substrate. The semiconductor chip has a front active area facing towards, and a metallized back surface facing away from, the laminar substrate. An encapsulation of LDS material on the laminar substrate encapsulates the semiconductor chip with the metallized back surface of the semiconductor chip exposed at an outer surface of the encapsulation of LDS material. Electrically conductive lines and first vias are structured in the region of LDS material to electrically connect to the front active area of the semiconductor chip. A thermally conductive layer is plated over the outer surface of the encapsulation of LDS material in contact with the metallized back surface of the semiconductor chip. A heat extractor body of thermally conductive material is coupled in heat transfer relationship with the thermally conductive layer.