公开(公告)号：US20220149859A1

公开(公告)日：2022-05-12

申请号：US17501112

申请日：2021-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Marzia Annovazzi ,  Alessandro Cannone ,  Enrico Ferrara ,  Gea Donzelli ,  Paolo Turbanti

IPC: H03M1/10 ,  H03M1/06

Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

公开(公告)号：US11658674B2

公开(公告)日：2023-05-23

申请号：US17501112

申请日：2021-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Marzia Annovazzi ,  Alessandro Cannone ,  Enrico Ferrara ,  Gea Donzelli ,  Paolo Turbanti

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1071 ,  H03M1/0687

Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

公开(公告)号：US11575404B2

公开(公告)日：2023-02-07

申请号：US17480926

申请日：2021-09-21

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Lucia Maggio ,  Marzia Annovazzi ,  Diego Alagna

IPC: H04B1/44 ,  H04L25/02

Abstract: A communication system has a galvanic isolation link coupling a first circuit to a second circuit. The first circuit transmits first data signals to the second circuit and receives second data signals from the second circuit in response to the first data signals. The data signals are transmitted in consecutive time slots of a determined time duration via the galvanic isolation link. The first data signals include polling signals transmitted from the first circuit to the second circuit during consecutive time slots, and on-demand access requests transmitted from the first circuit to the second circuit. The second data signals include status response signals transmitted from the second circuit to the first circuit in response to polling signals received from the first circuit, and access response signals transmitted from the second circuit to the first circuit in response to access requests received from the first circuit.