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公开(公告)号：US20240159819A1
公开(公告)日：2024-05-16
申请号：US17987379
申请日：2022-11-15
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Alessandro Cannone , Enrico Ferrara , Luigi Piscitelli
IPC: G01R31/28 , G01R31/3167 , G01R31/319
CPC classification number: G01R31/2834 , G01R31/3167 , G01R31/31926
Abstract: A circuit includes: first analog-to-digital converters (ADCs) configured to be coupled to respective ones of first sensors; a first multiplexer (MUX) coupled to output terminals of the first ADCs; a second MUX configured to be coupled to second sensors which are redundant sensors for the first sensors; a second ADC coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal; a first checker circuit configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches coupled between respective ones of the input terminals of the second MUX and a reference voltage node.
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公开(公告)号：US11658674B2
公开(公告)日：2023-05-23
申请号：US17501112
申请日：2021-10-14
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Marzia Annovazzi , Alessandro Cannone , Enrico Ferrara , Gea Donzelli , Paolo Turbanti
CPC classification number: H03M1/1071 , H03M1/0687
Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.
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Patent Agency Ranking
公开(公告)号：US12164000B2
公开(公告)日：2024-12-10
申请号：US17460657
申请日：2021-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Cannone , Enrico Ferrara , Nicola Errico , Gea Donzelli
IPC: G01R31/3167 , G01R31/28 , G01R31/317
Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.
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4.发明公开公开(公告)号：US20230170803A1
公开(公告)日：2023-06-01
申请号：US18154167
申请日：2023-01-13
Applicant: STMicroelectronics S.r.l.
Inventor： Enrico Ferrara , Luca Morinelli
CPC classification number: H02M3/158 , H02M1/08 , H02M3/1566 , H02M1/0019
Abstract: An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.
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公开(公告)号：US11581808B2
公开(公告)日：2023-02-14
申请号：US17244406
申请日：2021-04-29
Applicant: STMicroelectronics S.r.l.
Inventor： Enrico Ferrara , Luca Morinelli
Abstract: An embodiment buck converter control circuit comprises an error amplifier configured to generate an error signal based on a feedback signal and a reference signal, a pulse generator circuit configured to generate a pulsed signal having switching cycles set to high and low as a function of the error signal, a driver circuit configured to generate a drive signal for an electronic switch of the buck converter as a function of the pulsed signal, a variable load, connected between two output terminals of the buck converter, configured to absorb a current based on a control signal, and a detector circuit configured to monitor a first signal indicative of an output current provided by the buck converter and a second signal indicative of a negative transient of the output current, and verify whether the second signal indicates a negative transient of the output current.
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公开(公告)号：US11563319B1
公开(公告)日：2023-01-24
申请号：US17490285
申请日：2021-09-30
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Cignoli , Nicola Errico , Paolo Vilmercati , Stefano Castorina , Enrico Ferrara
Abstract: Disclosed herein is a single integrated circuit chip with a main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. The safety area is internally powered by an internal regulated voltage generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage while protecting against shorts of the external line delivering the external voltage. The safety area includes protection circuits that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits serving to protect against shorts of the external line delivering the external analog signals.
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公开(公告)号：US20220149859A1
公开(公告)日：2022-05-12
申请号：US17501112
申请日：2021-10-14
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Marzia Annovazzi , Alessandro Cannone , Enrico Ferrara , Gea Donzelli , Paolo Turbanti
Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.
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