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公开(公告)号：US12164000B2
公开(公告)日：2024-12-10
申请号：US17460657
申请日：2021-08-30
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro Cannone , Enrico Ferrara , Nicola Errico , Gea Donzelli
IPC: G01R31/3167 , G01R31/28 , G01R31/317
Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.
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公开(公告)号：US11742789B2
公开(公告)日：2023-08-29
申请号：US17535176
申请日：2021-11-24
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Vanni Poletto , Paolo Vilmercati , Marco Cignoli
CPC classification number: H02P27/12 , H02P27/085
Abstract: In an embodiment, an electronic circuit includes: a controller configured to produce a pulse-width-modulated (PWM) signal to control a first current of an electrical load; a redundant current measurement circuit configured to measure the first current and provide first and second current measurement signal; a monitor circuit coupled to the redundant current measurement circuit, the monitor circuit configured to assert a current monitor signal in response to the first and second current measurement signals being found to be matching with each other, wherein the monitor circuit is configured to: detect an absence of the asserted current monitor signal prior to expiry of a threshold time interval, and in response to detecting the absence of the asserted current monitor signal, force the controller to produce, prior to expiry of the threshold time interval, a first PWM signal pulse having a controlled duty-cycle.
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公开(公告)号：US20240159819A1
公开(公告)日：2024-05-16
申请号：US17987379
申请日：2022-11-15
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Alessandro Cannone , Enrico Ferrara , Luigi Piscitelli
IPC: G01R31/28 , G01R31/3167 , G01R31/319
CPC classification number: G01R31/2834 , G01R31/3167 , G01R31/31926
Abstract: A circuit includes: first analog-to-digital converters (ADCs) configured to be coupled to respective ones of first sensors; a first multiplexer (MUX) coupled to output terminals of the first ADCs; a second MUX configured to be coupled to second sensors which are redundant sensors for the first sensors; a second ADC coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal; a first checker circuit configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches coupled between respective ones of the input terminals of the second MUX and a reference voltage node.
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公开(公告)号：US20220190585A1
公开(公告)日：2022-06-16
申请号：US17454228
申请日：2021-11-09
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Antonio Giordano , Orazio Pennisi , Leonardo Pedone , Luca Finazzi
Abstract: A circuit includes comparator circuitry to sense a current through a load and compare the intensity of the current with a comparison threshold which can be set to a first, lower threshold value and a second, higher threshold value. Logic circuitry receives from the comparator circuitry a comparison signal having a first value or a second value based on whether the intensity is lower or higher than the comparison threshold. The logic circuitry is configured to assert a first overcurrent event signal or a second overcurrent event signal based on the comparison signal having the first value or the second value and the comparison threshold set to the first or second threshold value.
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公开(公告)号：US11563319B1
公开(公告)日：2023-01-24
申请号：US17490285
申请日：2021-09-30
Applicant: STMicroelectronics S.r.l.
Inventor： Marco Cignoli , Nicola Errico , Paolo Vilmercati , Stefano Castorina , Enrico Ferrara
Abstract: Disclosed herein is a single integrated circuit chip with a main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. The safety area is internally powered by an internal regulated voltage generated by an internal voltage regulator that generates the internal regulated voltage from an external voltage while protecting against shorts of the external line delivering the external voltage. The safety area includes protection circuits that level shift external analog signals downward in voltage for monitoring within the safety area, the protection circuits serving to protect against shorts of the external line delivering the external analog signals.
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Patent Agency Ranking
公开(公告)号：US20220149859A1
公开(公告)日：2022-05-12
申请号：US17501112
申请日：2021-10-14
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Marzia Annovazzi , Alessandro Cannone , Enrico Ferrara , Gea Donzelli , Paolo Turbanti
Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.
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公开(公告)号：US12038799B2
公开(公告)日：2024-07-16
申请号：US17903753
申请日：2022-09-06
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Luigi Sole , Rossella Gaudiano , Marta Cantarini , Nicola Errico , Antonio Giordano
IPC: G06F1/32 , G06F1/3206 , G06F1/3296
CPC classification number: G06F1/3206 , G06F1/3296
Abstract: A system basis chip is described. The system basis chip comprises a power supply circuit configured to receive an input voltage and generate a plurality of voltages, and a control circuit. Specifically, the power supply circuit is configured to selectively switch on a first and a second voltage of the voltages as a function of a control signal. The control circuit measures a resistance value of an external resistor connected to a terminal and selects one of a plurality of configurations as a function of the measured resistance value, wherein a first configuration indicates that said first voltage should be switched on before said second voltage and a second configuration indicates that said second voltage should be switched on before said first voltage. Accordingly, the control circuit may generate the control signal in order to switch on in sequence the first and the second voltage according to the selected configuration.
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公开(公告)号：US20220200509A1
公开(公告)日：2022-06-23
申请号：US17535176
申请日：2021-11-24
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Vanni Poletto , Paolo Vilmercati , Marco Cignoli
Abstract: In an embodiment, an electronic circuit includes: a controller configured to produce a pulse-width-modulated (PWM) signal to control a first current of an electrical load; a redundant current measurement circuit configured to measure the first current and provide first and second current measurement signal; a monitor circuit coupled to the redundant current measurement circuit, the monitor circuit configured to assert a current monitor signal in response to the first and second current measurement signals being found to be matching with each other, wherein the monitor circuit is configured to: detect an absence of the asserted current monitor signal prior to expiry of a threshold time interval, and in response to detecting the absence of the asserted current monitor signal, force the controller to produce, prior to expiry of the threshold time interval, a first PWM signal pulse having a controlled duty-cycle.
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公开(公告)号：US11979143B2
公开(公告)日：2024-05-07
申请号：US17870173
申请日：2022-07-21
Applicant: STMicroelectronics S.r.l.
Inventor： Nicola Errico , Valerio Bendotti , Luca Finazzi , Gaudenzia Bagnati
CPC classification number: H03K17/162 , H02M3/158 , H03K2217/0063 , H03K2217/0072 , H03K2217/0081
Abstract: A circuit includes a high-side transistor pair and a low-side transistor pair having a common intermediate node. The high-side transistor pair includes a first transistor having a control node and a current flowpath therethrough configured to provide a current flow line between a supply voltage node and the intermediate node, and a second transistor having a current flowpath therethrough coupled to the control node of the first transistor. The low-side transistor pair includes a third transistor having a control node and a current flowpath therethrough configured to provide a current flow line between the intermediate node and the reference voltage node, and a fourth transistor having a current flowpath therethrough coupled to the control node of the third transistor. Testing circuitry is configured to be coupled to at least one of the second transistor and the fourth transistor to apply thereto a test-mode signal.
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公开(公告)号：US11789048B2
公开(公告)日：2023-10-17
申请号：US17340559
申请日：2021-06-07
Applicant: STMicroelectronics S.r.l.
Inventor： Vanni Poletto , Nicola Errico , Paolo Vilmercati , Marco Cignoli , Vincenzo Salvatore Genna , Diego Alagna
IPC: G01R19/165 , H01H47/02 , H01H47/32
CPC classification number: G01R19/1659 , H01H47/02 , H01H47/325
Abstract: An embodiment circuit comprises high-side and low-side switches arranged between supply and reference nodes, and having an intermediate node. A switching control signal is applied with opposite polarities to the high-side and low-side switches. An inductive load is coupled between the intermediate node and one of the supply and reference nodes. Current sensing circuitry is configured to sample a first value of the load current flowing in one of the high-side and low-side switches before a commutation of the switching control signal, sample a second value of the load current flowing in the other of the high-side and low-side switches after the commutation of the switching control signal, sample a third value of the load current flowing in the other of the high-side and low-side switches after the second sampling, and generate a failure signal as a function of the first, second and third sampled values of the load current.
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