公开(公告)号：US12164000B2

公开(公告)日：2024-12-10

申请号：US17460657

申请日：2021-08-30

Applicant: STMicroelectronics S.r.l.

Inventor： Alessandro Cannone ,  Enrico Ferrara ,  Nicola Errico ,  Gea Donzelli

IPC: G01R31/3167 ,  G01R31/28 ,  G01R31/317

Abstract: Disclosed herein is a single integrated circuit chip including main logic that operates a vehicle component such as a valve driver. Isolated from the main logic within the chip is a safety area that operates to verify proper operation of the main logic. A checker circuit within the chip outside of the safety area serves to verify proper operation of the checker circuit. The checker circuit receives signals from the safety circuit and uses combinatorial logic circuit to verify from those signals that the check circuit is operating properly.

公开(公告)号：US11658674B2

公开(公告)日：2023-05-23

申请号：US17501112

申请日：2021-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Marzia Annovazzi ,  Alessandro Cannone ,  Enrico Ferrara ,  Gea Donzelli ,  Paolo Turbanti

IPC: H03M1/10 ,  H03M1/06

CPC classification number: H03M1/1071 ,  H03M1/0687

Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

公开(公告)号：US20240345987A1

公开(公告)日：2024-10-17

申请号：US18756821

申请日：2024-06-27

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Oreggia ,  Alessandro Cannone ,  Diego Alagna ,  Marcello Raimondi

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4022

Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.

公开(公告)号：US20240159819A1

公开(公告)日：2024-05-16

申请号：US17987379

申请日：2022-11-15

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Alessandro Cannone ,  Enrico Ferrara ,  Luigi Piscitelli

IPC: G01R31/28 ,  G01R31/3167 ,  G01R31/319

CPC classification number: G01R31/2834 ,  G01R31/3167 ,  G01R31/31926

Abstract: A circuit includes: first analog-to-digital converters (ADCs) configured to be coupled to respective ones of first sensors; a first multiplexer (MUX) coupled to output terminals of the first ADCs; a second MUX configured to be coupled to second sensors which are redundant sensors for the first sensors; a second ADC coupled to an output terminal of the second MUX, the first MUX and the second MUX being controlled by a selection signal; a first checker circuit configured to compare a first data at an output terminal of the first MUX with a second data at an output terminal of the second ADC; and a plurality of switches coupled between respective ones of the input terminals of the second MUX and a reference voltage node.

公开(公告)号：US12174252B2

公开(公告)日：2024-12-24

申请号：US18324583

申请日：2023-05-26

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Diego Alagna ,  Alessandro Cannone

IPC: G01R31/3177 ,  G01R31/317 ,  G06F1/08

Abstract: A first circuit is coupled to a second circuit via a communication link. The first circuit generates a first validation signal, a second validation signal, and control signals, and transmits the first and second validation signals to the second circuit via the communication link. The second circuit validates the control signals based on the first and second binary validation signals. The validating includes: verifying that when the first validation signal has a first value, the second validation signal has a second value different from the first value; verifying that when the second validation signal has the first value, the first validation signal has the second value; verifying detection of a transition edge of the first validation signal within a threshold number of clock cycles; and verifying detection of a transition edge of the second validation signal within the threshold number of clock cycles.

公开(公告)号：US20220149859A1

公开(公告)日：2022-05-12

申请号：US17501112

申请日：2021-10-14

Applicant: STMicroelectronics S.r.l.

Inventor： Nicola Errico ,  Marzia Annovazzi ,  Alessandro Cannone ,  Enrico Ferrara ,  Gea Donzelli ,  Paolo Turbanti

IPC: H03M1/10 ,  H03M1/06

Abstract: In an embodiment, a circuit includes N sensing channels. Each channel includes a first main sensing node and a second redundancy sensing node paired therewith. N analog-to-digital converters (ADCs) are coupled to the first sensing nodes, with digital processing circuits coupled to the N ADCs. A pair of multiplexers are coupled to the second sensing nodes and to the N ADCs with a further ADC coupled to the output of the second multiplexer. An error checking circuit is coupled to the outputs of the second multiplexer and the further ADC to compare, at each time window in a sequence of N time windows, a first digital value and a second digital value resulting from conversion to digital of: an analog sensing signal at one of the first sensing nodes, and an analog sensing signal at the second sensing node paired with the selected one of the first sensing nodes.

公开(公告)号：US12056080B2

公开(公告)日：2024-08-06

申请号：US17732114

申请日：2022-04-28

Applicant: STMicroelectronics S.r.l.

Inventor： Daniele Oreggia ,  Alessandro Cannone ,  Diego Alagna ,  Marcello Raimondi

IPC: G06F13/42 ,  G06F13/364 ,  G06F13/40

CPC classification number: G06F13/4291 ,  G06F13/364 ,  G06F13/4022

Abstract: A battery management system includes: a controller; a master battery management integrated circuit (BMIC) device coupled to the controller and configured to communicate with the controller through a standard Serial Peripheral Interface (SPI) protocol; and a first slave BMIC device and a second slave BMIC device that are connected in a daisy chain configuration and communicating through Isolated SPI interfaces, where the first slave BMIC device is coupled to the master BMIC through an Isolated SPI interface, where the Isolated SPI interface uses a differential signal comprising a positive signal and a complementary negative signal, where a bit frame of the positive signal includes a bit period followed by an idle period having a same duration as the bit period, where the first slave BMIC device and the second slave BMIC device are configured to be coupled to a first battery pack and a second battery pack, respectively.