公开(公告)号：US20170170795A1

公开(公告)日：2017-06-15

申请号：US15156155

申请日：2016-05-16

Applicant: STMICROELECTRONICS S.R.L.

Inventor： Marco GARBARINO ,  Roberto MODAFFARI ,  Germano NICOLLINI

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F3/3027 ,  H03F3/45183 ,  H03F3/45475 ,  H03F3/45659 ,  H03F2200/129 ,  H03F2203/45008 ,  H03F2203/45112 ,  H03F2203/45134 ,  H03F2203/45418 ,  H03F2203/45601

Abstract: An amplifier includes a first input branch and a second input branch that form a differential input stage and a current mirror connected to the differential input. The current mirror is governed as a function of a common mode feedback signal applied to a control node of the current mirror. A second, amplification, stage includes a branch flowing through which is a current, which is a function of the current that flows in the first input branch, and is in turn connected to a first output branch. A capacitive element is coupled between the control node and the second stage. The circuit is symmetrical with respect to the input stage.

公开(公告)号：US20220416743A1

公开(公告)日：2022-12-29

申请号：US17839335

申请日：2022-06-13

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto MODAFFARI ,  Paolo PESENTI ,  Mario MAIORE ,  Tiziano CHIARILLO

IPC: H03F3/70 ,  G01R27/26

Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.

公开(公告)号：US20220345150A1

公开(公告)日：2022-10-27

申请号：US17721110

申请日：2022-04-14

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Roberto MODAFFARI ,  Paolo PESENTI

IPC: H03M3/00

Abstract: A delta-sigma modulator includes a quantizer, a signal propagation path including a plurality of cascaded integrators coupled between the input node and the quantizer, and a feedback network including a plurality of digital-to-analog converters. In a calibration mode of operation, a first digital-to-analog converter of the plurality of digital-to-analog converters of the feedback network receives a signal including a periodic alternated digital sequence, the first digital-to-analog converter being coupled to a first integrator of the plurality of cascaded integrators, integrators of the plurality of cascaded integrators other than the first integrator operate in a gain mode of operation, the delta-sigma modulator generates a digital test signal at an output of the quantizer based on the signal including the periodic alternated digital sequence, and calibration circuitry generates a calibration signal based on the digital test signal and a reference digital word.

公开(公告)号：US20220263481A1

公开(公告)日：2022-08-18

申请号：US17665399

申请日：2022-02-04

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto MODAFFARI ,  Germano NICOLLINI

IPC: H03F3/45

Abstract: A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.

公开(公告)号：US20240275347A1

公开(公告)日：2024-08-15

申请号：US18634675

申请日：2024-04-12

Applicant: STMicroelectronics S.r.l.

Inventor： Roberto MODAFFARI ,  Paolo PESENTI ,  Mario MAIORE ,  Tiziano CHIARILLO

IPC: H03F3/70 ,  G01R27/26 ,  H03F3/45

CPC classification number: H03F3/70 ,  G01R27/2605 ,  H03F3/45968 ,  H03F2200/375

Abstract: A circuit includes an amplifier, a bias voltage node, and a first set of switches configured, based on a first reset signal having a first value, to couple first and second input nodes to the bias voltage node and to couple first and second output nodes of the amplifier. First and second feedback branches each include a respective RC network including a plurality of capacitances. The first and second feedback branches further include a second set of switches intermediate input nodes and the capacitances, and a third set of switches intermediate input nodes and the plurality of capacitances. These switches selectively couple the capacitances to the input nodes and output nodes, based on a second reset signal having a first value. The second reset signal keeps the first value for a determined time interval exceeding a time interval in which the first reset signal has the first value.

公开(公告)号：US20220173751A1

公开(公告)日：2022-06-02

申请号：US17677511

申请日：2022-02-22

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Roberto MODAFFARI ,  Paolo PESENTI ,  Germano NICOLLINI

IPC: H03M3/00

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.

公开(公告)号：US20210242878A1

公开(公告)日：2021-08-05

申请号：US17163230

申请日：2021-01-29

Applicant: STMICROELECTRONICS S.r.l.

Inventor： Roberto MODAFFARI ,  Paolo PESENTI ,  Germano NICOLLINI

IPC: H03M3/00

Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.