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公开(公告)号：US20220263481A1
公开(公告)日：2022-08-18
申请号：US17665399
申请日：2022-02-04
Applicant: STMicroelectronics S.r.l.
Inventor： Roberto MODAFFARI , Germano NICOLLINI
IPC: H03F3/45
Abstract: A circuit for startup of a multi-stage amplifier circuit includes a pair of input nodes and at least two output nodes configured to be coupled to a multi-stage amplifier circuit. A startup differential stage includes a differential pair of transistors having respective control terminals coupled to the pair of input nodes, and each transistor in the differential pair of transistors has a respective current path therethrough between a respective output node and a common source terminal. The startup differential stage is configured to sense a common mode voltage drop at a first differential stage of the multi-stage amplifier circuit. Current mirror circuitry includes a plurality of transistors coupled to the common terminal of the differential pair of transistors and coupled to two output nodes of the at least two output nodes.
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公开(公告)号：US20240106401A1
公开(公告)日：2024-03-28
申请号：US18369583
申请日：2023-09-18
Applicant: STMicroelectronics S.r.l.
Inventor： Germano NICOLLINI , Michele VAIANA
CPC classification number: H03F3/45475 , H03F1/26 , H03F3/45273 , H03F2200/261
Abstract: A measurement system, featuring first and second capacitances, and switching, control, and measurement circuits, charges/discharges the capacitances during normal operation. The switching and control circuits periodically connect a first terminal of the first capacitance to a first voltage and a reference voltage, and a first terminal of the second capacitance to a second voltage and the reference voltage. The second terminal of the first capacitance and the second terminal of the second capacitance are connected to the input terminals of the differential integrator, the charge difference between the capacitances being transferred to the differential integrator. A comparator triggers when the output signal of the differential integrator exceeds the hysteresis threshold of the comparator. Two decoupling capacitances are connected between the input of the comparator and the output of the differential integrator, and two reset phases are used to store various disturbances to these decoupling capacitances, improving precision.
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公开(公告)号：US20180342993A1
公开(公告)日：2018-11-29
申请号：US15984942
申请日：2018-05-21
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Alberto CATTANI , Germano NICOLLINI , Alessandro GASPARINI
CPC classification number: H03F3/2173 , G01R1/30 , G01R19/0092 , H03F3/45273 , H03F2200/261 , H03F2200/393 , H03F2200/456 , H03F2200/462 , H03F2200/474 , H03F2200/477 , H03F2200/483
Abstract: A switching amplifier, such as a Class D amplifier, includes a current sensing circuit. The current sensing circuit is formed by replica loop circuits that are selectively coupled to corresponding output inverter stages of the switching amplifier. The replica loop circuits operated to produce respective replica currents of the output currents generated by the output inverter stages. A sensing circuitry is coupled to receive the replica currents from the replica loop circuits and operates to produce an output sensing signal as a function of the respective replica currents.
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公开(公告)号：US20220337198A1
公开(公告)日：2022-10-20
申请号：US17720502
申请日：2022-04-14
Applicant: STMicroelectronics S.r.l.
Inventor： Alessandro BERTOLINI , Germano NICOLLINI
Abstract: An amplifier circuit includes a first input stage with a differential input transistor pair and a second gain stage having an output node coupled to a load. A node in the first gain stage is coupled to the output node in the second gain stage. A feedback line couples the output node to the control node of a first transistor of the differential input transistor pair. Current mirror circuitry is coupled to a current flow path through a further transistor in the second gain stage and includes a sensing node configured to produce a sensing signal indicative of the current supplied to the load. The sensing signal at the sensing node is directly fed back to the control node of the first transistor of the differential input transistor pair to provide a zero in the loop transfer function that is matched to and tracks and cancels out a load-dependent pole.
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公开(公告)号：US20220173751A1
公开(公告)日：2022-06-02
申请号：US17677511
申请日：2022-02-22
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Roberto MODAFFARI , Paolo PESENTI , Germano NICOLLINI
IPC: H03M3/00
Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
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Patent Agency Ranking
公开(公告)号：US20210349491A1
公开(公告)日：2021-11-11
申请号：US17380542
申请日：2021-07-20
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Germano NICOLLINI
Abstract: A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.
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公开(公告)号：US20210242878A1
公开(公告)日：2021-08-05
申请号：US17163230
申请日：2021-01-29
Applicant: STMICROELECTRONICS S.r.l.
Inventor： Roberto MODAFFARI , Paolo PESENTI , Germano NICOLLINI
IPC: H03M3/00
Abstract: A delta-sigma modulation circuit has a sampling period and, in operation, generates a delta-sigma modulated signal based on the analog input signal. The delta-sigma modulation circuit includes: a first integrator; an analog-to-digital converter; a feedback-loop coupled between an input of the first integrator and the output interface; a second integrator coupled between the first integrator and the analog-to-digital converter. The delta-sigma modulation circuit has loop-delay compensation circuitry having a plurality of switches. The loop delay compensation circuitry, in operation, controls the plurality of switches based on a time interval of a duration of half the sampling period and generates a loop-delay compensation signal.
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公开(公告)号：US20190113946A1
公开(公告)日：2019-04-18
申请号：US16160405
申请日：2018-10-15
Applicant: STMicroelectronics S.r.l.
Inventor： Germano NICOLLINI , Stefano POLESEL
CPC classification number: G05F3/265 , G05F3/225 , G05F3/30 , H03F3/45475 , H03F2200/129 , H03F2203/45116 , H03F2203/45528
Abstract: A first current proportional to absolute temperature flows in a first current line through a first p-n junction and a second p-n junction arranged in series. A cascaded arrangement of p-n junctions is coupled to the second p-n junction and includes a further p-n junction with a current flowing therethrough that has a third order proportionality on absolute temperature. A differential circuit has a first input coupled to the further p-n junction and a second input coupled to a current mirror from the first p-n junction, with the differential circuit configured to generate a bandgap voltage with a low temperature drift from a sum of first voltage (that is PTAT) derived from the first current and a second voltage (that is PTAT3) derived from the third current.
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公开(公告)号：US20190036518A1
公开(公告)日：2019-01-31
申请号：US16043346
申请日：2018-07-24
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Germano NICOLLINI
Abstract: A comparator circuit is implemented using a simple comparator core having two gain stages integrated in a single circuit block. The circuit operates with improved speed and resolution in comparison to a conventional continuous-time comparator. Offset trimming allows for the crossing time of the comparator to be adjusted close to an ideal crossing time.
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公开(公告)号：US20210165438A1
公开(公告)日：2021-06-03
申请号：US16950267
申请日：2020-11-17
Applicant: STMicroelectronics S.r.l.
Inventor： Stefano RAMORINI , Germano NICOLLINI
Abstract: A bandgap circuit includes a supply node as well as a first and second bipolar transistors having jointly coupled base terminal at a bandgap node providing a bandgap voltage. First and second current generators are coupled to the supply node and supply mirrored first and second currents, respectively, to first and second circuit nodes. A third circuit node is coupled to the first bipolar transistor via a first resistor and coupled to ground via a second resistor, respectively. The third circuit node is also coupled to the second bipolar transistor so that the second resistor is traversed by a current which is the sum of the currents through the bipolar transistors. A decoupling stage intermediate the current generators and the bipolar transistors includes first and second cascode decoupling transistors having jointly coupled control terminals receiving a bias voltage sensitive to the bandgap voltage.
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