公开(公告)号：US20040073749A1

公开(公告)日：2004-04-15

申请号：US10270753

申请日：2002-10-15

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS, S.A.

Inventor： Sivagnanam Parthasarathy ,  Andrew Cofler ,  Lionel Chaverot

IPC: G06F012/00

CPC classification number: G06F9/381 ,  G06F9/30181 ,  G06F9/325 ,  G06F9/3875 ,  G06F12/0864 ,  G06F12/0877 ,  G06F2212/1028 ,  Y02D10/13

Abstract: For instruction clusters for which no significant performance penalty is incurred, such as execution of hardware loops, a processor automatically and dynamically switches to a pipelined two-cycle access to an associated associative cache rather than a single-cycle access. An access involving more than one cycle uses less power because only the hit way within the cache memory is accessed rather than all ways within the indexed cache line. To maintain performance, the single-cycle cache access is utilized in all remaining instructions. In addition, where instruction clusters within a hardware loop fit entirely within a pre-fetch buffer, the cache sub-system is idled for any remaining iterations of the hardware loop to further reduce power consumption.

Abstract translation: 对于不会产生显着性能损失（如执行硬件循环）的指令集，处理器自动和动态切换到流水线的两周期访问关联的关联高速缓存而不是单周期访问。 涉及多个周期的访问使用更少的功率，因为​​只有高速缓存中的命中方式被访问，而不是索引的高速缓存行内的所有方式。 为了保持性能，在所有剩余指令中使用单周期高速缓存访​​问。 此外，在硬件环路内的指令集合完全适合预取缓冲器的情况下，高速缓存子系统对于硬件循环的任何剩余迭代都是空闲的，以进一步降低功耗。

公开(公告)号：US20020124044A1

公开(公告)日：2002-09-05

申请号：US10082816

申请日：2002-02-25

Applicant: STMicroelectronics S.A.

Inventor： Andrew Cofler ,  Anne Merlande ,  Sebastien Ferroussat

IPC: G06F015/16

CPC classification number: G06F9/3804 ,  G06F9/30094 ,  G06F9/3836 ,  G06F9/3842

Abstract: A processor includes a program memory containing program instructions, and a processor core including several processing units and a central unit. The central unit, upon receipt of a program instruction, issues corresponding instructions to the various processing units. The processor core is clocked by a clock signal. A branching instruction received by the central unit, in the course of a current cycle, is processed in the course of the current cycle.

Abstract translation: 处理器包括包含程序指令的程序存储器和包括若干处理单元和中央单元的处理器核心。 中央单元在接收到程序指令时，向各种处理单元发出相应的指令。 处理器内核由时钟信号计时。 在当前周期的过程中，由中央单元接收的分支指令在当前周期的过程中被处理。

公开(公告)号：US20020174385A1

公开(公告)日：2002-11-21

申请号：US10021269

申请日：2001-12-12

Applicant: STMicroelectronics S.A.

Inventor： Andrew Cofler ,  Laurent Wojcieszak ,  Arnaud Dehamel ,  Isabelle Sename

IPC: H02H003/05

CPC classification number: G06F11/3632 ,  G06F9/30072 ,  G06F11/3648

Abstract: A computer system for executing instructions having assigned guard indicators, comprises instruction supply circuitry, pipelined execution units for receiving instructions from the supply circuitry together with at least one guard indicator selected from a set of guard indicators, the execution unit including a master guard value store containing master values for the guard indicators, and circuitry for resolving the guard values in the execution pipeline and providing a signal to indicate whether the pipeline is committed to the execution of the instruction, and an emulator having watch circuitry for effecting a watch on selected instructions supplied to the execution pipeline and synchronising circuitry for correlating resolution of the guard indicator of each selected instruction with a program count for that instruction.

Abstract translation: 一种用于执行具有分配的保护指示器的指令的计算机系统，包括指令提供电路，用于从供应电路接收指令的流水线执行单元以及从一组保护指示器中选择的至少一个保护指示符，所述执行单元包括主保护值存储 包括用于保护指示器的主值，以及用于解析执行流水线中的保护值的电路，以及提供用于指示流水线是否被提交到执行指令的信号的模块，以及具有用于对所选指令进行监视的监视电路的仿真器 提供给执行流水线和同步电路，用于将每个所选指令的保护指示符的分辨率与该指令的程序计数相关。

公开(公告)号：US20020147901A1

公开(公告)日：2002-10-10

申请号：US10083629

申请日：2002-02-26

Applicant: STMicroelectronics S.A.

Inventor： Andrew Cofler

IPC: G06F009/00

CPC classification number: G06F9/3814 ,  G06F9/383 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/3889

Abstract: A processing unit is associated with a first FIFO-type memory and with a second FIFO-type memory. Each instruction for loading memory stored data into a register within the processing unit is stored in the first FIFO-type memory, and other operative instructions are stored in the second FIFO-type memory. An operative instruction involving the register is removed from the second FIFO-type memory if no loading instruction which is earlier in time, and intended to modify a value of the register associated with this operative instruction is present in the first FIFO-type memory. In the presence of such an earlier loading instruction, the operative instruction is removed from the second FIFO-type memory only after the loading instruction has been removed from the first FIFO-type memory.

Abstract translation: 处理单元与第一FIFO型存储器和第二FIFO型存储器相关联。 用于将存储器存储的数据加载到处理单元内的寄存器的每个指令被存储在第一FIFO型存储器中，并且其它操作指令被存储在第二FIFO型存储器中。 如果在第一FIFO型存储器中不存在用于修改与该操作指令相关联的寄存器的值的时间上的加载指令，则从第二FIFO型存储器移除涉及寄存器的操作指令。 在存在这种较早的加载指令的情况下，仅在从第一FIFO型存储器移除了加载指令之后，将操作指令从第二FIFO型存储器中移除。