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公开(公告)号:US20180239384A1
公开(公告)日:2018-08-23
申请号:US15693214
申请日:2017-08-31
Inventor: Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
CPC classification number: G05F3/262 , G05F1/46 , H03F3/16 , H03F3/195 , H03F2200/294
Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
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公开(公告)号:US20250055492A1
公开(公告)日:2025-02-13
申请号:US18929262
申请日:2024-10-28
Inventor: Danika Perrin , Sandrine Nicolas
IPC: H04B1/16
Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
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公开(公告)号:US10359800B2
公开(公告)日:2019-07-23
申请号:US15693214
申请日:2017-08-31
Inventor: Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
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公开(公告)号:US20180152142A1
公开(公告)日:2018-05-31
申请号:US15589814
申请日:2017-05-08
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Michel Ayraud , Sandrine Nicolas
CPC classification number: H03F1/0205 , H03F1/223 , H03F1/308 , H03F3/193 , H03F3/3022 , H03F2200/06 , H03F2200/09 , H03F2200/129 , H03F2200/18 , H03F2200/21 , H03F2200/294 , H03F2200/42 , H03F2200/451 , H03F2200/462 , H03F2200/481 , H03F2200/498 , H03F2200/534 , H03F2200/555 , H03F2203/30027 , H03F2203/30031 , H03F2203/30039 , H03F2203/30084 , H03F2203/30111 , H03F2203/30117 , H04B1/40
Abstract: An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.
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公开(公告)号:US20150077166A1
公开(公告)日:2015-03-19
申请号:US14479795
申请日:2014-09-08
Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS
Inventor: Thierry Masson , Sandrine Nicolas , Colette Morche
CPC classification number: H02M3/06 , G05F5/00 , H03F3/45959 , H04L25/0292
Abstract: A receiver circuit for a differential input signal, may include a divider bridge having first and second ends, a midpoint therebetween, and intermediate points on either side of the midpoint. The divider bridge is coupled to receive the differential input signal at the first and second ends. A current generator is coupled to the divider bridge and configured to generate compensation currents associated respectively with components of the differential input signal. The divider bridge is configured to receive the compensation currents respectively at the intermediate points, and generate a compensated differential signal between the intermediate points.
Abstract translation: 用于差分输入信号的接收器电路可以包括具有第一端和第二端,其中间点和中点两侧的中间点的分隔桥。 分压器桥耦合以在第一端和第二端接收差分输入信号。 电流发生器耦合到分压器桥并且被配置为产生分别与差分输入信号的分量相关联的补偿电流。 分压器桥被配置为分别在中间点处接收补偿电流,并在中间点之间产生经补偿的差分信号。
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公开(公告)号:US12155406B2
公开(公告)日:2024-11-26
申请号:US17881749
申请日:2022-08-05
Inventor: Danika Perrin , Sandrine Nicolas
Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
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公开(公告)号:US10979063B2
公开(公告)日:2021-04-13
申请号:US16862297
申请日:2020-04-29
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Sandrine Nicolas , Damien Giot , Serge Ramet , Reiner Welk
Abstract: An electronic circuit comprises capacitive structures that are connected to one or a plurality of nodes, where each of the capacitive structures is formed by a capacitor or by a plurality of capacitors electrically connected in parallel. The electronic circuit further comprises additional capacitors that are each connected to the one or plurality of nodes. For at least one distance between capacitors, the capacitive structures have a same average of values defined, for each capacitor of each capacitive structure, by the number of capacitors of the circuit connected to the one or plurality of nodes and located at the distance from the capacitor of the capacitive structure.
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公开(公告)号:US10063189B2
公开(公告)日:2018-08-28
申请号:US15589814
申请日:2017-05-08
Applicant: STMicroelectronics (Grenoble 2) SAS
Inventor: Michel Ayraud , Sandrine Nicolas
CPC classification number: H03F1/0205 , H03F1/223 , H03F1/308 , H03F3/193 , H03F3/3022 , H03F2200/06 , H03F2200/09 , H03F2200/129 , H03F2200/18 , H03F2200/21 , H03F2200/294 , H03F2200/42 , H03F2200/451 , H03F2200/462 , H03F2200/481 , H03F2200/498 , H03F2200/534 , H03F2200/555 , H03F2203/30027 , H03F2203/30031 , H03F2203/30039 , H03F2203/30084 , H03F2203/30111 , H03F2203/30117 , H04B1/40
Abstract: An amplification device includes an amplification stage having a transconductance amplification transistor and an output terminal. A biasing circuit is configured to bias in common mode the output terminal to a bias potential obtained on the basis of a voltage present between the gate and the source of the amplification transistor, and to compensate for parasitic variations of the voltage present between the gate and the source of the amplification transistor.
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公开(公告)号:US20230056937A1
公开(公告)日:2023-02-23
申请号:US17881749
申请日:2022-08-05
Inventor: Danika Perrin , Sandrine Nicolas
IPC: H04B1/16
Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
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公开(公告)号:US20230018356A1
公开(公告)日:2023-01-19
申请号:US17812062
申请日:2022-07-12
Inventor: Hugo Gicquel , Sandrine Nicolas , Cedric Rechatin , Reiner Welk
IPC: H03F3/193
Abstract: In an embodiment an amplifier includes a first MOS transistor having a drain connected to an output of the amplifier and a source coupled to a first node configured to receive a first power supply potential, a first capacitive element connected between an input of the amplifier and a gate of the first MOS transistor, a first current source connecting the drain of the first MOS transistor to a second node configured to receive a second power supply potential and a resistive element and a second capacitive element connected in parallel between the gate and the drain of the first MOS transistor, the resistive element including a switched capacitor.
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