公开(公告)号：US20240096620A1

公开(公告)日：2024-03-21

申请号：US18466542

申请日：2023-09-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Bilel Saidi

IPC: H01L21/02 ,  H01L29/04

CPC classification number: H01L21/02667 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L29/04

Abstract: An embodiment provides a method of forming a semiconductor device. A first silicon layer is deposited in a trench of a semiconductor substrate as an amorphous layer. A second silicon layer is deposited on top of and in contact with the first silicon layer as a polysilicon layer. After depositing the second silicon layer, the first silicon layer includes polysilicon having an average grain size different than an average grain size of the second silicon layer. A third semiconductor layer is deposited on top of and in contact with the second silicon layer to at least partially fill the trench.

公开(公告)号：US11251053B2

公开(公告)日：2022-02-15

申请号：US16990556

申请日：2020-08-11

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Joel Schmitt ,  Bilel Saidi ,  Sylvain Joblot

IPC: H01L21/00 ,  H01L21/3205 ,  H01L21/285 ,  H01L21/321 ,  H01L21/3215 ,  H01L23/528

Abstract: An electrode is included in a base substrate. A trench is produced in the base substrate. The trench is filled with an annealed amorphous material to form the electrode. The electrode is made of a crystallized material which includes particles that are implanted into a portion of the electrode that is located adjacent the front-face side of the base substrate.