公开(公告)号：US20150287689A1

公开(公告)日：2015-10-08

申请号：US14743072

申请日：2015-06-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon ,  Julien Cuzzocrea

IPC: H01L23/00 ,  H01L23/528 ,  H01L23/48

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13657 ,  H01L2224/13684 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.

Abstract translation: 集成电路芯片包括衬底管芯和集成电路以及形成在衬底管芯的正面上的前部电互连网络的层。 由导电材料制成的本地电连接通孔形成在基板模具的孔中。 通孔连接到电互连网络的连接部分。 由导电材料制成的电连接柱形成在电连接通孔的后部。 局部外部保护层至少部分地覆盖电连接通孔和电连接柱。

公开(公告)号：US09455239B2

公开(公告)日：2016-09-27

申请号：US14743072

申请日：2015-06-18

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Laurent-Luc Chapelon ,  Julien Cuzzocrea

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/48 ,  H01L23/528

CPC classification number: H01L24/13 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L2224/0401 ,  H01L2224/0501 ,  H01L2224/0502 ,  H01L2224/05099 ,  H01L2224/05548 ,  H01L2224/05556 ,  H01L2224/0556 ,  H01L2224/05571 ,  H01L2224/05599 ,  H01L2224/1147 ,  H01L2224/13014 ,  H01L2224/13016 ,  H01L2224/13025 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/13565 ,  H01L2224/13657 ,  H01L2224/13684 ,  H01L2924/00014 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2224/05552

Abstract: An integrated circuit chip includes a substrate die and integrated circuits and a layer incorporating a front electrical interconnect network formed on a front face of the substrate die. A local electrical connection via made of an electrically conductive material is formed in a hole of the substrate die. The via is linked to a connection portion of the electrical interconnect network. An electrical connection pillar made of an electrically conductive material is formed on a rear part of the electrical connection via. A local external protection layer at least partly covers the electrical connection via and the electrical connection pillar.