公开(公告)号：US20220384721A1

公开(公告)日：2022-12-01

申请号：US17751190

申请日：2022-05-23

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal GOURAUD ,  Laurent FAVENNEC

IPC: H01L45/00 ,  H01L27/24

Abstract: A memory cell is manufactured by: (a) forming a stack comprising a first layer made of a phase change material and a second layer made of a conductive material; (b) forming a mask on the stack covering only the memory cell location; and (c) etching portions of the stack not covered by the first mask. The formation of the mask covering only the memory cell location comprises defining a first mask extending in a row direction for each row of memory cell locations and then patterning the first mask in a column direction for each column of memory cell locations.

公开(公告)号：US20220028725A1

公开(公告)日：2022-01-27

申请号：US17496411

申请日：2021-10-07

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pascal GOURAUD ,  Delia RISTOIU

IPC: H01L21/762 ,  H01L29/06

Abstract: A substrate includes a first solid semiconductor region and a second semiconductor on insulator region. First and second cavities are simultaneously formed in the first and second regions, respectively, of the substrate using etching processes in two steps which form an upper portion and a lower portion of each cavity. The first and second cavities will each have a step at a level of an upper surface of the insulator of the second semiconductor on insulator region. A further oxidation of the first cavity produces a rounded or cut-off area for the upper portion.

公开(公告)号：US20240178055A1

公开(公告)日：2024-05-30

申请号：US18509190

申请日：2023-11-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Thierno Moussa BAH ,  Pascal GOURAUD ,  Patrick GROS D'AILLON ,  Emilie PREVOST

IPC: H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/768 ,  H01L29/94

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02178 ,  H01L21/30617 ,  H01L21/30625 ,  H01L21/76831 ,  H01L29/945

Abstract: The present description concerns a method of manufacturing an insulating trench in a substrate, for an electronic device, comprising the following successive steps: (a) filling a trench formed in the substrate with a first insulating material; (b) depositing a first etch stop layer on the first material; (c) depositing a second layer of a second insulating material on the first etch stop layer; (d) etching down to the etch stop layer; and (e) depositing a third layer made of a third tight material.

公开(公告)号：US20230178479A1

公开(公告)日：2023-06-08

申请号：US18075087

申请日：2022-12-05

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Marios BARLAS ,  Pascal GOURAUD

IPC: H01L23/522 ,  H01L21/768

CPC classification number: H01L23/5226 ,  H01L21/76834 ,  H01L21/76897

Abstract: A method is presented for manufacturing an insulated conductive via. The via crosses a first stack of layers to reach a first layer. A first cavity is formed partially extending into the first stack of layers. A second stack of layers is formed over the first stack of layers and in the first cavity. The second stack of layers includes an etch stop layer and an insulating layer. A second cavity is then formed extending completely through first and second stacks of layers to reach the first layer. An insulating liner then covers the walls and bottom of the second cavity. The insulating liner is then anisotropically etched, and the second cavity is filled by a conductive material forming the core of the via.